Replace uses of new *Init with *Init::get. This hides the allocation
implementation so that we can unique Inits in various ways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136486 91177308-0d34-0410-b5e6-96231b3b80d8
Make all of the RecTy constructors private, and use get() factory
methods instead. Return singleton instances when it makes sense.
ListTy instance pointers are stored in the element RecTy instance.
BitsRecTy instance pointers, one per length, are stored in a static vector.
Also unique DefInit instances. A Record has a unique DefInit which
has a unique RecordRecTy instance.
This saves some 200k-300k RecTy allocations when parsing ARM.td. It
reduces TableGen's heap usage by almost 50%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135399 91177308-0d34-0410-b5e6-96231b3b80d8
Manage Inits in a FoldingSet. This provides several benefits:
- Memory for Inits is properly managed
- Duplicate Inits are folded into Flyweights, saving memory
- It enforces const-correctness, protecting against certain classes
of bugs
The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen. This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen had diagnostic printers sprinkled about in a few places. Pull them
together into a single location in Error.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133568 91177308-0d34-0410-b5e6-96231b3b80d8
A RegisterTuples instance is used to synthesize super-registers by
zipping together lists of sub-registers. This is useful for generating
pseudo-registers representing register sequence constraints like 'two
consecutive GPRs', or 'an even-odd pair of floating point registers'.
The RegisterTuples def can be used in register set operations when
building register classes. That is the only way of accessing the
synthesized super-registers.
For example, the ARM QQ register class of pseudo-registers could have
been formed like this:
// Form pairs Q0_Q1, Q2_Q3, ...
def QQPairs : RegisterTuples<[qsub_0, qsub_1],
[(decimate QPR, 2),
(decimate (shl QPR, 1), 2)]>;
def QQ : RegisterClass<..., (add QQPairs)>;
Similarly, pseudo-registers representing '3 consecutive D-regs with
wraparound' look like:
// Form D0_D1_D2, D1_D2_D3, ..., D30_D31_D0, D31_D0_D1.
def DSeqTriples : RegisterTuples<[dsub_0, dsub_1, dsub_2],
[(rotl DPR, 0),
(rotl DPR, 1),
(rotl DPR, 2)]>;
TableGen automatically computes aliasing information for the synthesized
registers.
Register tuples are still somewhat experimental. We still need to see
how they interact with MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133407 91177308-0d34-0410-b5e6-96231b3b80d8
Targets that need to change the default allocation order should use the
AltOrders mechanism instead. See the X86 and ARM targets for examples.
The allocation_order_begin() and allocation_order_end() methods have been
replaced with getRawAllocationOrder(), and there is further support
functions in RegisterClassInfo.
It is no longer possible to insert arbitrary code into generated
register classes. This is a feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133332 91177308-0d34-0410-b5e6-96231b3b80d8
A register class can define AltOrders and AltOrderSelect instead of
defining method protos and bodies. The AltOrders lists can be defined
with set operations, and TableGen can verify that the alternative
allocation orders only contain valid registers.
This is currently an opt-in feature, and it is still possible to
override allocation_order_begin/end. That will not be true for long.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133320 91177308-0d34-0410-b5e6-96231b3b80d8
This prepares tablegen to compute register lists from set theoretic dag
expressions. This doesn't really make any difference as long as
Target.td still declares RegisterClass::MemberList as [Register].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133043 91177308-0d34-0410-b5e6-96231b3b80d8
Make the Elements vector private and expose an ArrayRef through
getOrder() instead. getOrder will eventually provide multiple
user-specified allocation orders.
Use the sorted member set for member and subclass tests. Clean up a lot
of ad hoc searches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133040 91177308-0d34-0410-b5e6-96231b3b80d8
Besides moving structural computations to CodeGenRegisters.cpp, this
also well-defines the order of these lists:
- Sub-register lists come from a pre-order traversal of the graph
defined by the SubRegs lists in the .td files.
- Super-register lists are topologically ordered so no register comes
before any of its sub-registers. When the sub-register graph is not a
tree, independent super-registers appear in numerical order.
- Lists of overlapping registers are ordered according to register
number.
This reverses the order of the super-regs lists, but nobody was
depending on that. The previous order of the overlaps lists was odd, and
it may have depended on the precise behavior of std::stable_sort.
The old computations are still there, but will be removed shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132881 91177308-0d34-0410-b5e6-96231b3b80d8
Create a new CodeGenRegBank class that will eventually hold all the code
that computes the register structure from Records.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132849 91177308-0d34-0410-b5e6-96231b3b80d8
I'll be moving some more code there to gather all of the
register-specific stuff in one place. Currently it is shared between
CodeGenTarget and RegisterInfoEmitter.
The plan is that CodeGenRegisters can compute the full register bank
structure while RegisterInfoEmitter only will handle the printing part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132788 91177308-0d34-0410-b5e6-96231b3b80d8
