Commit Graph

73885 Commits

Author SHA1 Message Date
Eric Christopher
d8cca66bb4 Handle fpcr register.
Part of PR10299 and rdar://9740322

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134653 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 22:54:12 +00:00
Eric Christopher
31b5f00c4e Add support for the X86 'l' constraint.
Fixes PR10149 and rdar://9738585

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134648 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 22:29:07 +00:00
Eric Christopher
09ad0b6894 Remove a FIXME. All of the standard ones are in the list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 22:29:03 +00:00
Akira Hatanaka
78d62b2c7f Remove unnecessary newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134645 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 22:06:18 +00:00
Devang Patel
476df5f64f Add DEBUG message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134643 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 21:44:42 +00:00
Evan Cheng
18fb1d35db Add Mode64Bit feature and sink it down to MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 21:06:52 +00:00
Bill Wendling
4ae970b393 Move a function out-of-line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134640 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 21:05:13 +00:00
Akira Hatanaka
03236be44a Rather than having printMemOperand change the way memory operands are printed
based on a modifier, split it into two functions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134637 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 20:54:20 +00:00
Akira Hatanaka
3014b2f322 This patch adds a flag in MCAsmInfo that indicates whether dwarf register
numbers should be printed instead of symbolic register names in
MCAsmStreamer::EmitRegisterName. This is necessary because some versions of
GNU assembler won't accept code in which symbolic register names are used in
cfi directives. There is no change in behavior unless the flag is explicitly
set to true by a backend.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 20:30:33 +00:00
Akira Hatanaka
17a2f8e551 Define class MipsMCInstLower.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134633 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 20:24:54 +00:00
Akira Hatanaka
aa08ea0530 Change visibility of MipsAsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 20:10:52 +00:00
Akira Hatanaka
2091a0d8d2 Define class MipsMCSymbolRefExpr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134629 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 19:27:22 +00:00
Akira Hatanaka
4d1abf1a38 Simplify MipsRegisterInfo::eliminateFrameIndex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134628 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 19:13:09 +00:00
Evan Cheng
4761a8d654 Rewrite comment in English.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134627 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 19:09:06 +00:00
Evan Cheng
963b03c1a9 Rename attribute 'thumb' to a more descriptive 'thumb-mode'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134626 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 19:05:12 +00:00
Akira Hatanaka
d3ac47f805 Reverse order of operands of address operand mem so that the base operand comes
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 18:57:00 +00:00
Akira Hatanaka
e280519ba6 Add missing return statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134622 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 18:27:36 +00:00
Devang Patel
9194c6716b If known DebugLocs do not match then two DBG_VALUE machine instructions are not identical. For example,
DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ]
        DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ]

These two MIs represent identical value, 3.31...,  for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134620 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 17:45:33 +00:00
Joerg Sonnenberger
f86b76ead7 Recognize mipseb as alias for mips for symmetry with mipsel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134617 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 16:53:52 +00:00
Oscar Fuentes
a8504111f6 Update CMake library dependencies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134616 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 16:33:00 +00:00
Douglas Gregor
7f358da70f Fix CMake build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134614 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 15:59:22 +00:00
Cameron Zwarich
375db7f39a The VMLA instruction and its friends are not actually fused; they're plain old
multiply-accumulate instructions with separate rounding steps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134609 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 08:28:52 +00:00
Evan Cheng
db068738e8 Sink feature IsThumb into MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134608 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 08:26:46 +00:00
Evan Cheng
347c50a293 Feature bits are 64-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134607 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 07:45:49 +00:00
Evan Cheng
0ddff1b535 Compute feature bits at time of MCSubtargetInfo initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 07:07:08 +00:00
Chris Lattner
cbd40f8357 type can be null
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134601 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 05:29:18 +00:00
Chris Lattner
7af453a3bd use a more efficient check for 'is metadata'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134599 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 05:12:37 +00:00
Bill Wendling
b99e412650 Use ArrayRef instead of a std::vector&.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134595 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 04:42:01 +00:00
Lang Hames
944520f38c Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. The
hasPredecessorHelper function allows predecessors to be cached to speed up
repeated invocations. This fixes PR10186.

X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X)

Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with
empty Visited and Worklist sets (i.e. no caching over invocations).

Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited
and Worklist to speed up repeated calls. The Visited set is searched for X
before going to the worklist to further search the DAG if necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 04:31:51 +00:00
Evan Cheng
39dfb0ff84 Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 03:55:05 +00:00
Bill Wendling
6a6b8c3e96 Add a target hook to encode the compact unwind information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134577 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 00:54:13 +00:00
Jim Grosbach
e727d67c58 Add isCodeGenOnly value to the CodeGenInstruction class.
So users of a CGI don't have to look up the value directly from the original
Record; just like the rest of the convenience values in the class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 00:48:02 +00:00
Lang Hames
d0626aacca Added a testcase for PR10220.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134573 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 00:36:02 +00:00
Devang Patel
7986289a9c Add DEBUG messages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134572 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 00:14:27 +00:00
Evan Cheng
94ca42ff04 Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 00:08:19 +00:00
Devang Patel
a4acb008cb Use DBG_VALUE location while inserting DBG_VALUE during alloca promotion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 00:05:58 +00:00
Jakub Staszak
447c40c402 Fix a bug in the "expect" intrinsic lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134566 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 23:50:16 +00:00
Eli Friedman
a38cfb2fce When tail-merging multiple blocks, make sure to correctly update the live-in list on the merged block to correctly account for the live-outs of all the predecessors. They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF).
Unfortunately, the testcase I have is large and confidential, so I don't have a test to commit at the moment; I'll see if I can come up with something smaller where this issue reproduces.

<rdar://problem/9716278>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 23:41:48 +00:00
Jim Grosbach
66c9ee7e6d Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134563 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 23:38:13 +00:00
Devang Patel
90369eb209 Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134561 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 23:26:18 +00:00
Devang Patel
a462d6e8eb Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 23:09:51 +00:00
Bill Wendling
2b2dc7c4be Clean up the #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 22:52:32 +00:00
Eric Christopher
882e1e1c5d Grammar and 80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134555 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 22:41:18 +00:00
Owen Anderson
9cbd7afb76 Fix a subtle issue in SmallVector. The following code did not work as expected:
vec.insert(vec.begin(), vec[3]);
The issue was that vec[3] returns a reference into the vector, which is invalidated when insert() memmove's the elements down to make space.  The method needs to specifically detect and handle this case to correctly match std::vector's semantics.

Thanks to Howard Hinnant for clarifying the correct behavior, and explaining how std::vector solves this problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134554 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 22:36:59 +00:00
Devang Patel
4fd3c5957e Handle cases where multiple dbg.declare and dbg.value intrinsics are tied to one alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134549 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 22:06:11 +00:00
Evan Cheng
78a9f138ae Add ARM MC registry routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134547 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 22:02:34 +00:00
Evan Cheng
ed5e355214 Rename files for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134546 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 22:01:53 +00:00
Nick Lewycky
298bc9a1a5 Add ImmutableList::contains(). Patch by Rui Paulo!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134545 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 21:59:48 +00:00
Jim Grosbach
d1689ae4b1 Mark ARM pseudo-instructions as isPseudo.
This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134540 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 21:35:46 +00:00
Jim Grosbach
806fcc040e Don't require pseudo-instructions to carry encoding information.
For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134539 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 21:33:38 +00:00