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Author SHA1 Message Date
Neil Booth
d1a23d573d If the power of 5 is exact, and the reciprocal exact, the error is zero not one half-ulps. This prevents an infinite loop in rare cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42950 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-13 03:34:08 +00:00
Evan Cheng
e765f8ed1a Fix test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42949 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-13 03:14:06 +00:00
Evan Cheng
5a68b285c0 New tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42948 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-13 03:10:54 +00:00
Evan Cheng
7f56625447 Local spiller optimization: 
Turn this:
movswl  %ax, %eax
movl    %eax, -36(%ebp)
xorl    %edi, -36(%ebp)
into
movswl  %ax, %eax
xorl    %edi, %eax
movl    %eax, -36(%ebp)
by unfolding the load / store xorl into an xorl and a store when we know the
value in the spill slot is available in a register. This doesn't change the
number of instructions but reduce the number of times memory is accessed.

Also unfold some load folding instructions and reuse the value when similar
situation presents itself.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42947 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-13 02:50:24 +00:00
Evan Cheng
106e8020bd Change unfoldMemoryOperand(). User is now responsible for passing in the 
register used by the unfolded instructions. User can also specify whether to
unfold the load, the store, or both.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42946 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-13 02:35:06 +00:00
Evan Cheng
fa9457276a Optionally create a MachineInstr without default implicit operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42945 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-13 02:23:01 +00:00
Arnold Schwaighofer
92226dd19f Correcting the corrections. Bad bad baaad emacs! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42935 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 21:53:12 +00:00
Arnold Schwaighofer
48abc5cf6b Corrected many typing errors. And removed 'nest' parameter handling 
for fastcc from X86CallingConv.td.  This means that nested functions
are not supported for calling convention 'fastcc'.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42934 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 21:30:57 +00:00
Dan Gohman
dfb6f13a45 Fix this test to not depend on the assembly output containing something 
that includes the string "st". This probably fixes the regression on
Darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42932 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 20:42:14 +00:00
Devang Patel
7b9e1d251f Dest type is always i8 *. This allows some simplification. 
Do not filter memmove.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42930 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 20:10:21 +00:00
Devang Patel
fff760296f t 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42929 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 20:04:24 +00:00
Gordon Henriksen
ed29a28464 Fix ocaml bindings for picky linkers. :) 
Thanks to Török Edvin for helping to track this down.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42927 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 19:48:13 +00:00
Duncan Sands
2e4d675d93 Due to the new tail call optimization, trampolines can no 
longer be created for fastcc functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42925 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 19:37:31 +00:00
Dale Johannesen
f646774edd ppc long double. Implement fabs and fneg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42924 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 19:02:17 +00:00
Evan Cheng
1c5d83c14e Update. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42922 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 18:22:55 +00:00
Chris Lattner
1ff2ddda08 don't use intptr_t without including it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42921 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 18:16:23 +00:00
Chris Lattner
a79dd432b3 Fix a bug in my patch last night that broke InstCombine/2007-10-12-Crash.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42920 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 18:05:47 +00:00
Dale Johannesen
6e63e09236 Implement i64->ppcf128 conversions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42919 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 17:52:03 +00:00
Chris Lattner
b89f67e3e6 Make this compute the correct offset, handling alignment of the element 
pointer correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42918 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 17:49:52 +00:00
Evan Cheng
48ff282dd4 Did mean to leave this in. INSERT_SUBREG isn't being coalesced yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42916 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 17:16:50 +00:00
Neil Booth
6ac7016eb1 Remove duplicate comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42913 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 16:05:57 +00:00
Neil Booth
96c7471b39 Implement correctly-rounded decimal->binary conversion, i.e. conversion 
from user input strings.

Such conversions are more intricate and subtle than they may appear;
it is unlikely I have got it completely right first time.  I would
appreciate being informed of any bugs and incorrect roundings you
might discover.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42912 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 16:02:31 +00:00
Neil Booth
5b8e0c5fd3 Remove a field that was never used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42911 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 15:35:10 +00:00
Neil Booth
7a951ca548 If we're trying to be arbitrary precision, unsigned char clearly won't cut it. Needed for dec->bin conversions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42910 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 15:33:27 +00:00
Neil Booth
1e8390d8d6 Don't attempt to mask no bits 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42909 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 15:31:31 +00:00
Dan Gohman
8ddde0a151 Change the names used for internal labels to use the current 
function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42908 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 14:53:36 +00:00
Dan Gohman
a9b511187b Fix some corner cases with vectors in copyToRegs and copyFromRegs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42907 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 14:33:11 +00:00
Dan Gohman
9e04c82c0e Add support to SplitVectorOp for powi, where the second operand 
is a scalar integer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42906 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 14:13:46 +00:00
Dan Gohman
f0d0089340 Mark vector ctpop, cttz, and ctlz as Expand on x86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42905 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 14:09:42 +00:00
Dan Gohman
a3f269f7f6 Mark vector pow, ctpop, cttz, and ctlz as Expand on PowerPC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42904 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 14:08:57 +00:00
Evan Cheng
52c7ff7067 Restrict EXTRACT_SUBREG coalescing to avoid negative performance impact. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42903 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 09:15:53 +00:00
Evan Cheng
37a073eab4 Doh. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42901 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 09:10:27 +00:00
Evan Cheng
dce05bc5ed EXTRACT_SUBREG test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42900 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 09:03:31 +00:00
Evan Cheng
32dfbeada7 EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG like 
(almost) a register copy. However, it always coalesced to the register of the
RHS (the super-register). All uses of the result of a EXTRACT_SUBREG are sub-
register uses which adds subtle complications to load folding, spiller rewrite,
etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42899 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 08:50:34 +00:00
Evan Cheng
10136e7c7f Some clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42898 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 08:45:27 +00:00
Evan Cheng
dad9db6a32 Cosmetic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42897 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 08:40:44 +00:00
Evan Cheng
3393f892c7 Fix typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42896 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 08:39:02 +00:00
Evan Cheng
f4a9c69ff6 Fold load / store into MOV32to32_ and MOV16to16_. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42895 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 08:38:01 +00:00
Evan Cheng
96aaa54529 Flag MOV32to32_ with EXTRACT_SUBREG. They should not be scheduled apart. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42894 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 07:55:53 +00:00
Arnold Schwaighofer
a8e8864094 Added missing -march=x86 flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42893 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 07:49:48 +00:00
Gabor Greif
f3cdf3e3ec eliminate warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42892 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 07:44:54 +00:00
Chris Lattner
6a94de2990 Fix some 80 column violations. 
Fix DecomposeSimpleLinearExpr to handle simple constants better.
Don't nuke gep(bitcast(allocation)) if the bitcast(allocation) will
fold the allocation.  This fixes PR1728 and Instcombine/malloc3.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42891 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 05:30:59 +00:00
Chris Lattner
cb324cfc32 testcase for PR1728 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42890 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 05:29:53 +00:00
Chris Lattner
886636445d make operator== work with non-equal sized bitvectors, as long as 
the extra bits are all zeros.  This allows  "010" and "010000" to be
treated as equal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42889 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 03:48:59 +00:00
Dale Johannesen
ca68aaa0e5 PPC long double. Implement a couple more conversions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42888 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 01:37:08 +00:00
Dan Gohman
ac9385a555 Add intrinsics for sin, cos, and pow. These use llvm_anyfloat_ty, and so 
may be overloaded with vector types. And add a testcase for codegen for
these.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42885 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-12 00:01:22 +00:00
Dan Gohman
8266952813 Codegen support for vector intrinsics. 
Factor out the code that expands the "nasty scalar code" for unrolling
vectors into a separate routine, teach it how to handle mixed
vector/scalar operands, as seen in powi, and use it for several operators,
including sin, cos, powi, and pow.

Add support in SplitVectorOp for fpow, fpowi and for several unary
operators.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42884 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-11 23:57:53 +00:00
Dale Johannesen
fcf4d24ffb Implement ppc long double->uint conversion. 
Make ppc long double constants print.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42882 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-11 23:32:15 +00:00
Dan Gohman
f96e4de403 Set ISD::FPOW to Expand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42881 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-11 23:21:31 +00:00
Dan Gohman
e54be10418 Add runtime library names for pow. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42880 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-11 23:09:10 +00:00