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447 Commits

Author SHA1 Message Date
Evan Cheng
d24165aa71 Spiller reuse test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41068 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-14 05:51:03 +00:00
Evan Cheng
1f808011e0 Now capable of rematerializing coalesced live intervals. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41061 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-13 23:54:16 +00:00
Dan Gohman
badb2d23d1 When x86 addresses matching exceeds its recursion limit, check to 
see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41049 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-13 20:03:06 +00:00
Chris Lattner
a45d9a15ba Fix PR1607 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41048 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-13 18:42:37 +00:00
Christopher Lamb
8441157f6e Fix test so it passes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41012 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 22:20:57 +00:00
Christopher Lamb
c59e52108b Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41010 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 21:48:46 +00:00
Christopher Lamb
b81337117c Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41007 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 21:18:25 +00:00
Dan Gohman
25ac7e8364 Fix EXTRACT_ELEMENT, EXTRACT_SUBVECTOR, and EXTRACT_VECTOR_ELT to 
use an intptr ValueType instead of i32 for the index operand in
getCopyToParts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40987 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 14:59:38 +00:00
Chris Lattner
3038778c1e allow this to pass on ppc hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40846 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-05 18:48:18 +00:00
Dan Gohman
7f55fcbc6b Fix the alignment requirements of several unpck and shuf instructions. 
Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40756 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 21:17:01 +00:00
Dan Gohman
73a902b228 Mark the SSE and MMX load instructions that 
X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle
with the isReMaterializable flag so that it is given a chance to handle
them. Without hoisting constant-pool loads from loops this isn't very
visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from
making a copy of the constant pool on the stack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40736 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 14:27:55 +00:00
Evan Cheng
0a2a515c5b Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40721 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 05:04:16 +00:00
Evan Cheng
911935a068 New test. Bogus implicit-def prevented a copy from being coalesced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40690 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 20:26:40 +00:00
Chris Lattner
b59e985cdb we're now handling this right :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40675 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 17:10:30 +00:00
Evan Cheng
ad076727f8 Requires SSE2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40657 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 00:10:12 +00:00
Dan Gohman
b1576f56c8 Change the x86 assembly output to use tab characters to separate the 
mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40648 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-31 20:11:57 +00:00
Evan Cheng
c64a1a921c Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40628 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-31 08:04:03 +00:00
Dan Gohman
d300622eba Re-apply 40504, but with a fix for the segfault it caused in oggenc: 
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40555 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-27 17:16:43 +00:00
Evan Cheng
3e22947d9a Reverting 40504 for now. It's breaking oggenc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40547 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-27 01:37:47 +00:00
Evan Cheng
42000ef6c7 Test case for PR1573. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40539 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-26 17:45:57 +00:00
Evan Cheng
77baf8e80e Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40536 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-26 17:07:03 +00:00
Dan Gohman
d3283832aa Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the 
x86 target, replacing them with the new alignment attributes on memory
references.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40504 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-26 00:31:09 +00:00
Dan Gohman
a394117bc0 Use movaps to load a v4f32 build_vector of all-constant values into a 
register instead of loading each element individually.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40478 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-24 22:55:08 +00:00
Dan Gohman
9bc5dce98d Update these regression tests to accomodate X86InstrSSE.td now using movups/movaps 
for everything.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40101 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-20 16:31:26 +00:00
Evan Cheng
7800479260 New test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40077 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-20 00:27:56 +00:00
Evan Cheng
66746741a7 New test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40073 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 23:53:50 +00:00
Evan Cheng
158622cca3 Try fixing it again. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40072 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 23:53:29 +00:00
Reid Spencer
9445e9aaa0 For PR1553: 
Change the keywords for the zext and sext parameter attributes to be 
zeroext and signext so they don't conflict with the keywords for the
instructions of the same name. This gets around the ambiguity.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40069 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 23:13:04 +00:00
Bill Wendling
3b1c0994a0 Don't need the "&&" to glue lines together. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40063 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 18:06:26 +00:00
Bill Wendling
74430e7b0e Testcase for PR1549 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40041 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 06:31:11 +00:00
Evan Cheng
ccb21fdbb6 New test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40020 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-18 21:39:16 +00:00
Dan Gohman
4106f3714e Implement initial memory alignment awareness for SSE instructions. Vector loads 
and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40015 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-18 20:23:34 +00:00
Dan Gohman
48613b930a It's not necessary to do rounding for alloca operations when the requested 
alignment is equal to the stack alignment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40004 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-18 16:29:46 +00:00
Evan Cheng
574470a561 Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39976 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-17 18:16:09 +00:00
Evan Cheng
89d1659cf2 Use push / pop for prologues and epilogues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39967 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-17 07:59:08 +00:00
Dale Johannesen
e7e7d0d7e3 Skeleton of post-RA scheduler; doesn't do anything yet. 
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39816 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-13 17:13:54 +00:00
Evan Cheng
d04e8ecf5f Add test case for PR1545. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39749 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-11 19:29:05 +00:00
Dan Gohman
743d3a7548 Change the peep for EXTRACT_VECTOR_ELT of BUILD_PAIR to look for 
the new CONCAT_VECTORS node type instead, as that's what legalize
uses now. And add a peep for EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38503 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 18:20:44 +00:00
Dan Gohman
02e25b70aa Add a regression test for folding spill code into scalar min and max. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38492 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 15:34:29 +00:00
Chris Lattner
ba7721633c force a cpu without SSE 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38466 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-09 17:35:18 +00:00
Chris Lattner
349d4c8d66 allow this to work on ppc-darwin 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38465 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-09 17:32:28 +00:00
Bill Wendling
93888428d4 Allow a GR64 to be moved into an MMX register via the "movd" instruction. 
Still need to have JIT generate this code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37863 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-04 00:19:54 +00:00
Dale Johannesen
9eed80cb12 New testcases for rev 37847 (PR's 1489 and 1505). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37848 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-03 00:58:37 +00:00
Dan Gohman
9212a8261f Add a basic test-case for passing and returning <4 x double> and 
<8 x float> values on X86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37845 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-02 16:23:47 +00:00
Dan Gohman
03de31acae New test case. DAGCombiner should be able to fold -sin(-x) 
in -enable-unsafe-fp-math mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37841 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-02 15:43:20 +00:00
Evan Cheng
00e7fed30d New test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37823 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-29 23:17:15 +00:00
Evan Cheng
cdc85a58a0 New test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37815 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-29 21:40:30 +00:00
John Criswell
e644ef7b09 Convert .cvsignore files 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37801 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-29 16:35:07 +00:00
Evan Cheng
97f5ccf682 New tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37787 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-29 00:27:18 +00:00
Evan Cheng
ad0a4c0be9 New test case: identity operation of RHS / LHS of a VECTOR_SHUFFLE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37637 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 00:06:08 +00:00