Commit Graph

9322 Commits

Author SHA1 Message Date
Nico Rieck
d56e7e198d Revert "Reuse %rax after calling __chkstk on win64"
This reverts commit 01f8d579f7.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185781 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-08 01:30:57 +00:00
Nico Rieck
01f8d579f7 Reuse %rax after calling __chkstk on win64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-07 16:48:39 +00:00
Nico Rieck
2b52880592 Proper va_arg/va_copy lowering on win64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185763 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-06 18:08:19 +00:00
Jakob Stoklund Olesen
f349a6e9e6 Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 13:54:20 +00:00
Jakob Stoklund Olesen
c93822901a Revert r185595-185596 which broke buildbots.
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 00:26:30 +00:00
Jakob Stoklund Olesen
62204220e1 Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 23:56:31 +00:00
Craig Topper
365ef0b197 Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185540 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 15:07:05 +00:00
Ulrich Weigand
716a94f0c9 [DebugInfo] Allow getDebugThreadLocalSymbol to return MCExpr
This allows getDebugThreadLocalSymbol to return a generic MCExpr
instead of just a MCSymbolRefExpr.

This is in preparation for supporting debug info for TLS variables
on PowerPC, where we need to describe the variable location using
a more complex expression than just MCSymbolRefExpr.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185460 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 18:47:09 +00:00
David Blaikie
a35ae96291 PR16493: DebugInfo with TLS on PPC crashing due to invalid relocation
Restrict the current TLS support to X86 ELF for now. Test that we don't
produce it on PPC & we can flesh that test case out with the right thing
once someone implements it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185389 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 21:45:25 +00:00
Ahmed Bougacha
27bf6e96a7 X86: POP*rmm: move address operand to (ins) from (outs).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185292 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-30 20:44:50 +00:00
Chad Rosier
a5545bc2b9 Fix an off-by-one error. Also make the code a little more explicit in what it
is trying to do.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-28 18:57:01 +00:00
David Blaikie
c084c0945b Integrate Assembler: Support X86_64_DTPOFF64 relocations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185131 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-28 04:24:32 +00:00
Nadav Rotem
e6dc376eec Get rid of the unused class member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-27 17:54:10 +00:00
Nadav Rotem
16d36a5cd1 CostModel: improve the cost model for load/store of non power-of-two types such as <3 x float>, which are popular in graphics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-27 17:52:04 +00:00
Benjamin Kramer
872bb36810 Don't cast away constness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185071 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-27 11:07:42 +00:00
Elena Demikhovsky
87070fe107 Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184931 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-26 10:55:03 +00:00
Arnold Schwaighofer
34eb2406b4 X86 cost model: Vectorizing integer division is a bad idea
radar://14057959

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184872 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 19:14:09 +00:00
Andrew Trick
b2b5dc642c Revert "Temporarily enable MI-Sched on X86."
This reverts commit 98a9b72e8c.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184823 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 02:48:58 +00:00
Andrew Trick
98a9b72e8c Temporarily enable MI-Sched on X86.
Sorry for the unit test churn. I'll try to make the change permanently
next time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:13:20 +00:00
Andrew Trick
0f2eec65fb Add MI-Sched support for x86 macro fusion.
This is an awful implementation of the target hook. But we don't have
abstractions yet for common machine ops, and I don't see any quick way
to make it table-driven.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184664 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-23 09:00:28 +00:00
Chad Rosier
5b3fca50a0 The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-22 18:37:38 +00:00
David Blaikie
1948910e31 DebugInfo: Don't lose unreferenced non-trivial by-value parameters
A FastISel optimization was causing us to emit no information for such
parameters & when they go missing we end up emitting a different
function type. By avoiding that shortcut we not only get types correct
(very important) but also location information (handy) - even if it's
only live at the start of a function & may be clobbered later.

Reviewed/discussion by Evan Cheng & Dan Gohman.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184604 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-21 22:56:30 +00:00
Andrew Trick
9b5575d55a Fix IMULX machine model. Multiple def operands require multiple SchedWrites.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184566 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-21 18:33:04 +00:00
Kevin Enderby
46d7de7a19 Update the X86 disassembler to use xacquire and xrelease when appropriate.
This is a bit tricky as the xacquire and xrelease hints use the same bytes,
0xf2 and 0xf3, as the repne and rep prefixes.

Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease
and repne/xacquire. So to make this work a boolean was added the
InternalInstruction struct as part of the Prefix state which is set with the
added logic in readPrefixes() when decoding an instruction to determine
if these prefix bytes are to be disassembled as xacquire or xrelease.  Then
we let the matcher pick the normal prefix instructionID and we change the
Opcode after that when it is set into the MCInst being created.

rdar://11019859


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184490 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 22:32:18 +00:00
Bill Wendling
ba54bca472 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 21:36:55 +00:00
Bill Wendling
ea44281d5d Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 20:51:24 +00:00
Nadav Rotem
ef2d9e3194 Fix 80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 20:41:52 +00:00
Stefanus Du Toit
23306deb92 Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184207 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 17:08:10 +00:00
Bill Wendling
99cb622041 Use pointers to the MCAsmInfo and MCRegInfo.
Someone may want to do something crazy, like replace these objects if they
change or something.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184175 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 07:20:20 +00:00
David Blaikie
0187e7a9ba DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-16 20:34:27 +00:00
Andrew Trick
a3d82ce19f Support BufferSize on ProcResGroup for unified MOp schedulers.
And add Sandybridge/Haswell resource buffers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-15 04:50:06 +00:00
Andrew Trick
a5ce5f36d3 Update machine models. Specify buffer sizes for OOO processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184033 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-15 04:50:02 +00:00
Andrew Trick
b86a0cdb67 Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-15 04:49:57 +00:00
Benjamin Kramer
d25ec760cb X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX equivalent.
Give it the right register format so we can also emit it when AVX is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183971 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-14 09:31:41 +00:00
Benjamin Kramer
19b30d56b2 X86: Make the cmov aliases work with intel syntax too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183907 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-13 15:45:24 +00:00
Patrik Hagglund
8fdb53dc5e Fix gcc -flto build, by adding LLVM_ATTRIBUTE_USED to
LLVMX86CompilationCallback2, called from inline asm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-12 08:45:39 +00:00
Eric Christopher
2a2bf795d2 Correct the def registers for the 8bit x86 divide instructions to
match the comments and what the instruction actually does. Noticed
on inspection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183809 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 23:41:44 +00:00
Eric Christopher
3ce2a98c89 Use the Copy we defined above here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183808 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 23:41:41 +00:00
Tim Northover
e5609f3732 X86: Stop LEA64_32r doing unspeakable things to its arguments.
Previously LEA64_32r went through virtually the entire backend thinking it was
using 32-bit registers until its blissful illusions were cruelly snatched away
by MCInstLower and 64-bit equivalents were substituted at the last minute.

This patch makes it behave normally, and take 64-bit registers as sources all
the way through. Previous uses (for 32-bit arithmetic) are accommodated via
SUBREG_TO_REG instructions which make the types and classes agree properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 20:43:49 +00:00
Elena Demikhovsky
40e071c1eb Removed PackedDouble domain from scalar instructions. Added more formats for the scalar stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183626 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-09 07:37:10 +00:00
Bill Wendling
a5e5ba611f Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183571 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 21:00:34 +00:00
Bill Wendling
1ce4985e01 Remove unused c'tor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183570 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:59:31 +00:00
Bill Wendling
6a2e7ac0b6 Cache the TargetLowering info object as a pointer.
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 00:43:09 +00:00
Michael Liao
9a508ef64a [PATCH] Fix VGATHER* operand constraints
Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."

---
[1] http://software.intel.com/sites/default/files/319433-014.pdf



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 18:12:26 +00:00
Rafael Espindola
6c1202c459 Handle relocations that don't point to symbols.
In ELF (as in MachO), not all relocations point to symbols. Represent this
properly by using a symbol_iterator instead of a SymbolRef. Update llvm-readobj
ELF's dumper to handle relocatios without symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 01:33:53 +00:00
Ahmed Bougacha
b8ce45752b X86: sub_xmm registers are 128 bits wide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183103 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 14:42:40 +00:00
Tim Northover
3ba14fab1b Revert r183069: "TMP: LEA64_32r fixing"
Very sorry, it was committed from the wrong branch by mistake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183070 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 10:23:46 +00:00
Tim Northover
4d3ace4da0 TMP: LEA64_32r fixing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183069 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 10:21:54 +00:00
Tim Northover
85c622d6b6 X86: change MOV64ri64i32 into MOV32ri64
The MOV64ri64i32 instruction required hacky MCInst lowering because it
was allocated as setting a GR64, but the eventual instruction ("movl")
only set a GR32. This converts it into a so-called "MOV32ri64" which
still accepts a (appropriate) 64-bit immediate but defines a GR32.
This is then converted to the full GR64 by a SUBREG_TO_REG operation,
thus keeping everyone happy.

This fixes a typo in the opcode field of the original patch, which
should make the legact JIT work again (& adds test for that problem).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183068 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 09:55:14 +00:00
Eric Christopher
34431085de Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as it
seems to have caused PR16192 and other JIT related failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183059 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 23:30:45 +00:00