Commit Graph

9322 Commits

Author SHA1 Message Date
Michael Liao
959ddbb5e0 Enhance bool simplifcation in X86 to handle more cases
This patch is revised based on patch from Victor Umansky
<victor.umansky@intel.com>. More cases are handled in X86's bool
simplification, i.e.
- SETCC_CARRY
- value is truncated to i1 with AND

As a by-product, PR5443 is also fixed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11 04:43:09 +00:00
Nico Rieck
18d49acdab MC: Support COFF image-relative MCSymbolRefs
Add support for the COFF relocation types IMAGE_REL_I386_DIR32NB and
IMAGE_REL_AMD64_ADDR32NB for 32- and 64-bit respectively. These are
similar to normal 4-byte relocations except that they do not include
the base address of the image.

Image-relative relocations are used for debug information (32-bit) and
SEH unwind tables (64-bit).

A new MCSymbolRef variant called 'VK_COFF_IMGREL32' is introduced to
specify such relocations. For AT&T assembly, this variant can be accessed
using the symbol suffix '@imgrel'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179240 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 23:28:17 +00:00
Kay Tiong Khoo
c92cc5d918 fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 21:52:25 +00:00
Kay Tiong Khoo
49bbb35dfc fixed to disassemble with tab after mnemonic rather than space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 21:17:58 +00:00
Preston Gurd
15b64d0e28 In the X86 back end, getMemoryOperandNo() returns the offset
into the operand array of the start of the memory reference descriptor.

Additional code in EncodeInstruction provides an additional adjustment.

This patch places that additional code in a separate function,
called getOperandBias, so that any caller of getMemoryOperandNo
can also call getOperandBias.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179211 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 20:11:59 +00:00
Chad Rosier
37c04bcff2 Tidy up, fix and simplify a few of the SMLocs. Prior to r179109 the Start SMLoc
wasn't always the start of the operand.  If there was a symbol reference, then
Start pointed to that token.  It's very likely there are other places that need
to be updated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179210 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 20:07:47 +00:00
Chad Rosier
b4d6a6574d Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179205 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 18:46:58 +00:00
Chad Rosier
ba69b36692 Reapply r179115, but use parsePrimaryExpression a little more judiciously.
Test cases that regressed due to r179115, plus a few more, were added in
r179182.  Original commit message below:

[ms-inline asm] Use parsePrimaryExpr in lieu of parseExpression if we need to
parse an identifier.  Otherwise, parseExpression may parse multiple tokens,
which makes it impossible to properly compute an immediate displacement.
An example of such a case is the source operand (i.e., [Symbol + ImmDisp]) in
the below example:

 __asm mov eax, [Symbol + ImmDisp]

Part of rdar://13611297

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179187 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 17:35:30 +00:00
Evan Cheng
3a6b7d38a7 __sincosf_stret returns sinf / cosf in bits 0:31 and 32:63 of xmm0, not in
xmm0 / xmm1.

rdar://13599493


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 01:26:07 +00:00
Chad Rosier
df1087061c Cleanup. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179129 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 20:58:48 +00:00
Chad Rosier
bad493e912 Cleanup. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179125 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 20:44:09 +00:00
Chad Rosier
3eb6d7fcd0 Revert r179115 as it looks to have killed the ASan tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 19:59:12 +00:00
Chad Rosier
d4727e3798 [ms-inline asm] Use parsePrimaryExpr in lieu of parseExpression if we need to
parse an identifier.  Otherwise, parseExpression may parse multiple tokens,
which makes it impossible to properly compute an immediate displacement.
An example of such a case is the source operand (i.e., [Symbol + ImmDisp]) in
the below example:

 __asm mov eax, [Symbol + ImmDisp]

The existing test cases exercise this patch.
rdar://13611297


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179115 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 19:34:59 +00:00
Chad Rosier
b976e407dc [ms-inline asm] Maintain a StringRef to reference a symbol in a parsed operand,
rather than deriving the StringRef from the Start and End SMLocs.

Using the Start and End SMLocs works fine for operands such as [Symbol], but
not for operands such as [Symbol + ImmDisp].  All existing test cases that
reference a variable exercise this patch.
rdar://13602265



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179109 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 17:53:49 +00:00
Arnold Schwaighofer
813456527e X86 cost model: Model cost for uitofp and sitofp on SSE2
The costs are overfitted so that I can still use the legalization factor.

For example the following kernel has about half the throughput vectorized than
unvectorized when compiled with SSE2. Before this patch we would vectorize it.

unsigned short A[1024];
double B[1024];
void f() {
  int i;
  for (i = 0; i < 1024; ++i) {
    B[i] = (double) A[i];
  }
}

radar://13599001

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179033 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 18:05:48 +00:00
Chad Rosier
6b369ceb58 [ms-inline asm] Add support for ImmDisp [ Symbol ] memory operands.
rdar://13521249


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179030 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 17:43:47 +00:00
Bill Wendling
13bbe1f52e Use the target options specified on a function to reset the back-end.
During LTO, the target options on functions within the same Module may
change. This would necessitate resetting some of the back-end. Do this for X86,
because it's a Friday afternoon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178917 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05 21:52:40 +00:00
Chad Rosier
e112453fc3 [ms-inline asm] Add support for numeric displacement expressions in bracketed
memory operands.

Essentially, this layers an infix calculator on top of the parsing state
machine.  The scale on the index register is still expected to be an immediate

 __asm mov eax, [eax + ebx*4]

and will not work with more complex expressions.  For example,

 __asm mov eax, [eax + ebx*(2*2)]

The plus and minus binary operators assume the numeric value of a register is
zero so as to not change the displacement.  Register operands should never
be an operand for a multiply or divide operation; the scale*indexreg
expression is always replaced with a zero on the operand stack to prevent
such a case.
rdar://13521380


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05 16:28:55 +00:00
Arnold Schwaighofer
2537f3c659 X86 cost model: Differentiate cost for vector shifts of constants
SSE2 has efficient support for shifts by a scalar. My previous change of making
shifts expensive did not take this into account marking all shifts as expensive.
This would prevent vectorization from happening where it is actually beneficial.

With this change we differentiate between shifts of constants and other shifts.

radar://13576547

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178808 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04 23:26:24 +00:00
Arnold Schwaighofer
6bf4f67641 CostModel: Add parameter to instruction cost to further classify operand values
On certain architectures we can support efficient vectorized version of
instructions if the operand value is uniform (splat) or a constant scalar.
An example of this is a vector shift on x86.

We can efficiently support

for (i = 0 ; i < ; i += 4)
  w[0:3] = v[0:3] << <2, 2, 2, 2>

but not

for (i = 0; i < ; i += 4)
  w[0:3] = v[0:3] << x[0:3]

This patch adds a parameter to getArithmeticInstrCost to further qualify operand
values as uniform or uniform constant.

Targets can then choose to return a different cost for instructions with such
operand values.

A follow-up commit will test this feature on x86.

radar://13576547

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04 23:26:21 +00:00
Arnold Schwaighofer
6b6050b229 X86 cost model: Vector shifts are expensive in most cases
The default logic does not correctly identify costs of casts because they are
marked as custom on x86.

For some cases, where the shift amount is a scalar we would be able to generate
better code. Unfortunately, when this is the case the value (the splat) will get
hoisted out of the loop, thereby making it invisible to ISel.

radar://13130673
radar://13537826

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03 21:46:05 +00:00
Timur Iskhodzhanov
eea35066ab Fix SRet for thiscall in i686-pc-win32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03 11:27:54 +00:00
Eric Christopher
f5ebc39fc5 Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178589 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02 23:06:40 +00:00
Chad Rosier
30c729b5d0 [ms-inline asm] Add support for parsing variables with namespace alias
qualifiers.

This patch only adds support for parsing these identifiers in the
X86AsmParser.  The front-end interface isn't capable of looking up
these identifiers at this point in time.  The end result is the
compiler now errors during object file emission, rather than at
parse time.  Test case coming shortly.
Part of rdar://13499009 and PR13340


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178566 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02 20:02:33 +00:00
Chad Rosier
146b8c2129 [fast-isel] Use the correct API to disable FastLowerArguments for Win64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178549 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02 16:31:41 +00:00
Andrew Trick
92142b3275 The divide unit is not pipeline, but it is still buffered.
Buffered means a later divide may be executed out-of-order while a
prior divide is sitting (buffered) in a reservation station.

You can tell it's not pipelined, because operations that use it
reserve it for more than one cycle:

def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
  let Latency = 25;
  let ResourceCycles = [1, 10];
}

We don't currently distinguish between an unpipeline operation and one
that is split into multiple micro-ops requiring the same unit. Except
that the later may have NumMicroOps > 1 if they also consume
issue/dispatch resources.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178519 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02 01:58:47 +00:00
Benjamin Kramer
13497b3aa7 X86TTI: Add accurate costs for itofp operations, based on the actual instruction counts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 10:23:49 +00:00
Benjamin Kramer
b8f0d89d05 X86: Promote sitofp <8 x i16> to <8 x i32> when AVX is available.
A vector sext + sitofp is a lot cheaper than 8 scalar conversions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178448 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31 12:49:15 +00:00
Benjamin Kramer
42734cfb41 Change '@SECREL' suffix to GAS-compatible '@SECREL32'.
'@SECREL' is what is used by the Microsoft assembler, but GNU as expects '@SECREL32'.
With the patch, the MC-generated code works fine in combination with a recent GNU as (2.23.51.20120920 here).

Patch by David Nadlinger!
Differential Revision: http://llvm-reviews.chandlerc.com/D429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178427 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 16:21:50 +00:00
Benjamin Kramer
74a4533a42 Remove the old CodePlacementOpt pass.
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 17:14:24 +00:00
Michael Liao
c26392aa5d Add support of RDSEED defined in AVX2 extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:41:26 +00:00
Michael Liao
258d9b7bc0 Enhance boolean simplification to handle 16-/64-bit RDRAND
- RDRAND always clears the destination value when a random value is not
  available (i.e. CF == 0). This value is truncated or zero-extended as
  the false boolean value to be returned. Boolean simplification needs
  to skip this 'zext' or 'trunc' node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:38:52 +00:00
Michael Liao
816f6d0ac7 Skip moving call address loading into callseq when targets prefer register indirect call.
To enable a load of a call address to be folded with that call, this
load is moved from outside of callseq into callseq. Such a moving
adds a non-glued node (that load) into a glued sequence. This non-glue
load is only removed when DAG selection folds them into a memory form
call instruction. When such instruction selection is disabled, it breaks
DAG schedule.

To prevent that, such moving is disabled when target favors register
indirect call.

Previous workaround disabling CALL32m/CALL64m insn selection is removed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178308 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:13:21 +00:00
Nadav Rotem
bad24f757d Add the X86 FMAs to the scheduling model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178303 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 22:54:45 +00:00
Nadav Rotem
59af9d0bf4 Add the Haswell machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178301 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 22:34:46 +00:00
Nadav Rotem
0b6a69d4a1 Remove the unused port from the SandyBridge machine model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178300 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 22:32:41 +00:00
Michael Liao
5a8386e1df Add ADX CPUID detection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178299 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 22:29:53 +00:00
Timur Iskhodzhanov
a46f82dbf9 Make Win32 put the SRet address into EAX, fixes PR15556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178291 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 21:30:04 +00:00
Preston Gurd
1fd36e41e4 This patch follows is a follow up to r178171, which uses the register
form of call in preference to memory indirect on Atom.

In this case, the patch applies the optimization to the code for reloading
spilled registers.

The patch also includes changes to sibcall.ll and movgs.ll, which were
failing on the Atom buildbot after the first patch was applied.

This patch by Sriram Murali.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178193 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27 23:16:18 +00:00
Chad Rosier
dd40e8cd54 [ms-inline asm] Add support of imm displacement before bracketed memory
expression.  Specifically, this syntax:

 ImmDisp [ BaseReg + Scale*IndexReg + Disp ] 

We don't currently support:

 ImmDisp [ Symbol ]

rdar://13518671


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27 21:49:56 +00:00
Preston Gurd
1edadea42f For the current Atom processor, the fastest way to handle a call
indirect through a memory address is to load the memory address into
a register and then call indirect through the register.

This patch implements this improvement by modifying SelectionDAG to
force a function address which is a memory reference to be loaded
into a virtual register.

Patch by Sriram Murali.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178171 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27 19:14:02 +00:00
Hal Finkel
e915047fed Fix typo (common to both X86 and PPC)
Thanks to Bill Schmidt for pointing this out during code review!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27 19:10:42 +00:00
Michael Liao
f8fd883fd3 Add XTEST codegen support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 22:47:01 +00:00
Michael Liao
0ca1a7f177 Add HLE target feature
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178082 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 22:46:02 +00:00
Jakob Stoklund Olesen
6b359ecd43 Enable SandyBridgeModel for all modern Intel P6 descendants.
All Intel CPUs since Yonah look a lot alike, at least at the granularity
of the scheduling models. We can add more accurate models for
processors that aren't Sandy Bridge if required. Haswell will probably
need its own.

The Atom processor and anything based on NetBurst is completely
different. So are the non-Intel chips.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178080 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 22:19:12 +00:00
Jakob Stoklund Olesen
b4f60e9f77 Annotate the remaining x86 instructions with SchedRW lists.
Now all x86 instructions that have itinerary classes also have SchedRW
lists. This is required before the new scheduling models can be used.

There are still unannotated instructions remaining, but they don't have
itinerary classes either.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178051 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 18:24:22 +00:00
Jakob Stoklund Olesen
75f6310dc9 Annotate x87 and mmx instructions with SchedRW lists.
This only covers the instructions that were given itinerary classes for
the Atom model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178050 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 18:24:20 +00:00
Jakob Stoklund Olesen
2bb3fcd490 Annotate control instructions with SchedRW lists.
This could definitely be more granular. I am not sure if it makes a
difference.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178049 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 18:24:17 +00:00
Jakob Stoklund Olesen
cdf7625960 Annotate the rest of X86InstrInfo.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178048 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 18:24:15 +00:00
Michael Liao
675eb3b9ac Add PREFETCHW codegen support
- Add 'PRFCHW' feature defined in AVX2 ISA extension



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 17:47:11 +00:00
Michael Liao
d4584c9e56 Revise alignment checking/calculation on 256-bit unaligned memory access
- It's still considered aligned when the specified alignment is larger
  than the natural alignment;
- The new alignment for the high 128-bit vector should be min(16,
  alignment) as the pointer is advanced by 16, a power-of-2 offset.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177947 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 23:50:10 +00:00
Jakob Stoklund Olesen
7ae14f3d97 Add a scheduling model for Intel Sandy Bridge microarchitecture.
The model isn't hooked up by this patch because the instruction set
isn't fully annotated yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177942 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 23:37:17 +00:00
Jakob Stoklund Olesen
68d832a04d Remove IIC_DEFAULT from X86Schedule.td
All the instructions tagged with IIC_DEFAULT had nothing in common, and
we already have a NoItineraries class to represent untagged
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177937 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 23:12:41 +00:00
Jakob Stoklund Olesen
b203ef3938 Annotate X86InstrCompiler.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177936 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 23:07:35 +00:00
Jakob Stoklund Olesen
8a9db4f9ad Annotate shifts and rotates with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177935 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 23:07:32 +00:00
NAKAMURA Takumi
a154371eca X86DisassemblerDecoder.c: Make this C89-compliant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177910 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 20:55:49 +00:00
NAKAMURA Takumi
8173c5e7c8 Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177909 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 20:55:43 +00:00
Dave Zarzycki
9b3939983f x86 -- add the XTEST instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 18:59:43 +00:00
Dave Zarzycki
97a80092d3 x86 -- disassemble the REP/REPNE prefix when needed
This fixes Apple bug: 13493622

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177887 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 18:59:38 +00:00
Jakob Stoklund Olesen
c1ea2c5d6d Add a WriteMicrocoded for ancient microcoded instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21 00:07:17 +00:00
Jakob Stoklund Olesen
3c987aead2 Model prefetches and barriers as loads.
It's not yet clear if these instructions need a more careful model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177599 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20 23:09:53 +00:00
Jakob Stoklund Olesen
eab5f7678b Add a catch-all WriteSystem SchedWrite type.
This is used for all the expensive system instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177598 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20 23:09:50 +00:00
Jakob Stoklund Olesen
dcb4d349b6 Annotate the remaining SSE MOV instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177592 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20 22:37:16 +00:00
Jakob Stoklund Olesen
2e9aadda63 Annotate SSE horizontal and integer instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177591 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20 22:37:13 +00:00
Michael Liao
f74e9bf650 Correct cost model for vector shift on AVX2
- After moving logic recognizing vector shift with scalar amount from
  DAG combining into DAG lowering, we declare to customize all vector
  shifts even vector shift on AVX is legal. As a result, the cost model
  needs special tuning to identify these legal cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177586 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20 22:01:10 +00:00
Jakob Stoklund Olesen
279ad470b6 Add some missing SSE annotations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177540 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20 16:56:39 +00:00
Jakob Stoklund Olesen
374a204f02 Annotate remaining IIC_BIN_* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177539 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20 16:56:36 +00:00
Michael Liao
42317ccb5f Fix PR15296
- Move SRA/SRL/SHL lowering support from DAG combination to DAG lowering
  to support extended 256-bit integer in AVX but not AVX2.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177478 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20 02:33:21 +00:00
Michael Liao
5c5f1908f0 Mark all variable shifts needing customizing
- Prepare moving logic from DAG combining into DAG lowering. There's no
  functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177477 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20 02:28:20 +00:00
Michael Liao
4b7ab12d93 Move scalar immediate shift lowering into a dedicated func
- no functionality change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20 02:20:36 +00:00
Jakob Stoklund Olesen
361706a718 Annotate various null idioms with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177461 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 23:23:31 +00:00
Jakob Stoklund Olesen
f2914c3b2b Annotate SSE float conversions with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177460 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 23:23:29 +00:00
Jakob Stoklund Olesen
fea666b540 Annotate X86InstrCMovSetCC.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 23:23:26 +00:00
Chad Rosier
811ddf64af [ms-inline asm] Move the immediate asm rewrite into the target specific
logic as a QOI cleanup.  No functional change.  Tests already in place.
rdar://13456414

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 21:58:18 +00:00
Jakob Stoklund Olesen
f36a4afaae Annotate X86InstrCompiler.td with SchedRW lists.
Add a new WriteZero SchedWrite type for the common dependency-breaking
instructions that clear a register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177442 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 21:16:56 +00:00
Chad Rosier
d3e7416de7 [ms-inline asm] Create a helper function, CreateMemForInlineAsm, that creates
an X86Operand, but also performs a Sema lookup and adds the sizing directive
when appropriate.  Use this when parsing a bracketed statement.  This is
necessary to get the instruction matching correct as well.  Test case coming
on clang side.
rdar://13455408

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177439 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 21:11:56 +00:00
Ulrich Weigand
58ebc04078 Remove an invalid and unnecessary Pat pattern from the X86 backend:
def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
            (MOV64rm tglobaltlsaddr :$dst)>;

This pattern is invalid because the MOV64rm instruction expects a
source operand of type "i64mem", which is a subclass of X86MemOperand
and thus actually consists of five MI operands, but the Pat provides
only a single MI operand ("tglobaltlsaddr" matches an SDnode of
type ISD::TargetGlobalTLSAddress and provides a single output).

Thus, if the pattern were ever matched, subsequent uses of the MOV64rm
instruction pattern would access uninitialized memory.  In addition,
with the TableGen patch I'm about to check in, this would actually be
reported as a build-time error.

Fortunately, the pattern does in fact never match, for at least two
independent reasons.

First, the code generator actually never generates a pattern of the
form (load (X86Wrapper (tglobaltlsaddr))).  For most combinations of
TLS and code models, (tglobaltlsaddr) represents just an offset that
needs to be added to some base register, so it is never directly
dereferenced.  The only exception is the initial-exec model, where
(tglobaltlsaddr) refers to the (pc-relative) address of a GOT slot,
which *is* in fact directly dereferenced: but in that case, the
X86WrapperRIP node is used, not X86Wrapper, so the Pat doesn't match.

Second, even if some patterns along those lines *were* ever generated,
we should not need an extra Pat pattern to match it.  Instead, the
original MOV64rm instruction pattern ought to match directly, since
it uses an "addr" operand, which is implemented via the SelectAddr
C++ routine; this routine is supposed to accept the full range of
input DAGs that may be implemented by a single mov instruction,
including those cases involving ISD::TargetGlobalTLSAddress (and
actually does so e.g. in the initial-exec case as above).

To avoid build breaks (due to the above-mentioned error) after the
TableGen patch is checked in, I'm removing this Pat here.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177426 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 19:49:52 +00:00
Nadav Rotem
b05130e1b2 Optimize sext <4 x i8> and <4 x i16> to <4 x i64>.
Patch by Ahmad, Muhammad T <muhammad.t.ahmad@intel.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177421 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 18:38:27 +00:00
Jakob Stoklund Olesen
a45a22758d Annotate X86InstrExtension.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177418 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 18:03:58 +00:00
Jakob Stoklund Olesen
528c761124 Annotate a lot of X86InstrInfo.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177417 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 18:03:55 +00:00
Chad Rosier
023c880220 [ms-inline asm] Move the size directive asm rewrite into the target specific
logic as a QOI cleanup.
rdar://13445327

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 17:32:17 +00:00
Chad Rosier
ee29c16890 [ms-inline asm] Avoid emitting a redundant sizing directive, if we've already
parsed one.  Test case coming shortly.
rdar://13446980

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177347 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 23:31:24 +00:00
Jakob Stoklund Olesen
9beae49622 Add SchedRW annotations to most of X86InstrSSE.td.
We hitch a ride with the existing OpndItins class that was used to add
instruction itinerary classes in the many multiclasses in this file.

Use the link provided by the X86FoldableSchedWrite.Folded to find the
right SchedWrite for folded loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177326 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 22:01:35 +00:00
Jakob Stoklund Olesen
30d25f0a30 Annotate X86 arithmetic instructions with SchedRW lists.
This new-style scheduling information is going to replace the
instruction iteneraries.

This also serves as a test case for Andy's fix in r177317.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177323 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 21:32:39 +00:00
Anton Korobeynikov
2ee4e428cc TLS support for MinGW targets.
MinGW is almost completely compatible to MSVC, with the exception of the _tls_array global not being available.

Patch by David Nadlinger!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 08:12:28 +00:00
Craig Topper
8ee1c1cfaf Post process ADC/SBB and use a shorter encoding if they use a sign extended immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177243 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 03:34:55 +00:00
Craig Topper
4bef961baf Refactor some duplicated code into helper functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177242 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 02:53:34 +00:00
Craig Topper
8647750dfb Add X86 code emitter support AVX encoded MRMDestReg instructions.
Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-16 03:44:31 +00:00
Jakob Stoklund Olesen
e0c489d22b Define more SchedWrites for annotating X86 instructions.
Since almost all X86 instructions can fold loads, use a multiclass to
define register/memory pairs of SchedWrites.

An X86FoldableSchedWrite represents the register version of an
instruction. It holds a reference to the SchedWrite to use when the
instruction folds a load.

This will be used inside multiclasses that define rr and rm instruction
versions together.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177210 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-16 00:02:17 +00:00
Eric Christopher
a286fc065a Silence anonymous type in anonymous union warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15 00:42:55 +00:00
Nadav Rotem
dd7a300c10 Unaligned loads should use the VMOVUPS opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 23:49:44 +00:00
Jakob Stoklund Olesen
488e4f445a Prepare for adding InstrSchedModel annotations to X86 instructions.
The new InstrSchedModel is easier to use than the instruction
itineraries. It will be used to model instruction latency and throughput
in modern Intel microarchitectures like Sandy Bridge.

InstrSchedModel should be able to coexist with instruction itinerary
classes, but for cleanliness we should switch the Atom processor model
to the new InstrSchedModel as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177122 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 22:42:17 +00:00
Chad Rosier
d9b306a477 [fast-isel] The X86FastISel::FastLowerArguments function doesn't properly handle
the win64 calling convention.
rdar://13423768

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177113 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 21:25:04 +00:00
Craig Topper
fdf168fbc4 Fix the name of a variable to match its declaration. Fixes build failure from r177014.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177015 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 07:47:43 +00:00
Craig Topper
9d3f3c5f40 Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177014 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 07:40:52 +00:00
Craig Topper
599521f167 Teach X86 MC instruction lowering that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177011 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 07:09:57 +00:00
Michael Liao
6f8c6852a0 Fix PR15309
- Fix the typo on type checking



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177010 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 06:57:42 +00:00
Kevin Enderby
12dccaed9c Fixes disassembler crashes on 2013 Haswell RTM instructions.
rdar://13318048


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11 21:17:13 +00:00
Tom Stellard
3ef5383b35 DAGCombiner: Use correct value type for checking legality of BR_CC v3
LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.

v2:
  - Expand more BR_CC value types for NVPTX

v3:
  - Expand correct BR_CC value types for Hexagon, Mips, and XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 15:36:57 +00:00
Benjamin Kramer
02c2ecf9f1 X86: Fold EXTRACT_SUBVECTORs of a BUILD_VECTOR into a smaller BUILD_VECTOR.
That can usually be lowered efficiently and is common in sandybridge code.
It would be nice to do this in DAGCombiner but we can't insert arbitrary
BUILD_VECTORs this late.

Fixes PR15462.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07 18:48:40 +00:00
Michael Liao
fe9dbe0066 Fix two remaining issue after fixing PR15355 when CMOV is not available
- Phi nodes should be replaced/updated after lowering CMOV into branch
  because 'mainMBB' updating operand in Phi node is changed.
- Add EFLAGS in livein before lowering the 2nd CMOV. It's necessary as
  we will reuse the EFLAGS generated before the 1st lowered CMOV, which
  won't clobber EFLAGS. However, we need explicitly specify that.
- '-attr=-cmov' test case are added.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176598 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07 01:01:29 +00:00
Michael Liao
c537f79dcd Fix PR15355
- Clear 'mayStore' flag when loading from the atomic variable before the
  spin loop
- Clear kill flag from one use to multiple use in registers forming the
  address to that atomic variable
- don't use a physical register as live-in register in BB (neither entry
  nor landing pad.) by copying it into virtual register

(patch by Cameron Zwarich)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176538 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-06 00:17:04 +00:00
David Sehr
6c4265a541 The current X86 NOP padding uses one long NOP followed by the remainder in
one-byte NOPs.  If the processor actually executes those NOPs, as it sometimes
does with aligned bundling, this can have a performance impact.  From my
micro-benchmarks run on my one machine, a 15-byte NOP followed by twelve
one-byte NOPs is about 20% worse than a 15 followed by a 12.  This patch
changes NOP emission to emit as many 15-byte (the maximum) as possible followed
by at most one shorter NOP.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176464 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 00:02:23 +00:00
Preston Gurd
9a2cfffdb6 Bypass Slow Divides
* Only apply divide bypass optimization when not optimizing for size. 
* Fixed bug caused by constant for 0 value of type Int32,
  used dividend type to generate the constant instead.
* For atom x86-64 apply the divide bypass to use 16-bit divides instead of
  64-bit divides when operand values are small enough.
* Added lit tests for 64-bit divide bypass.

Patch by Tyler Nowicki!




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176442 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04 18:13:57 +00:00
Arnold Schwaighofer
5f0d9dbdf4 X86 cost model: Adjust cost for custom lowered vector multiplies
This matters for example in following matrix multiply:

int **mmult(int rows, int cols, int **m1, int **m2, int **m3) {
  int i, j, k, val;
  for (i=0; i<rows; i++) {
    for (j=0; j<cols; j++) {
      val = 0;
      for (k=0; k<cols; k++) {
        val += m1[i][k] * m2[k][j];
      }
      m3[i][j] = val;
    }
  }
  return(m3);
}

Taken from the test-suite benchmark Shootout.

We estimate the cost of the multiply to be 2 while we generate 9 instructions
for it and end up being quite a bit slower than the scalar version (48% on my
machine).

Also, properly differentiate between avx1 and avx2. On avx-1 we still split the
vector into 2 128bits and handle the subvector muls like above with 9
instructions.
Only on avx-2 will we have a cost of 9 for v4i64.

I changed the test case in test/Transforms/LoopVectorize/X86/avx1.ll to use an
add instead of a mul because with a mul we now no longer vectorize. I did
verify that the mul would be indeed more expensive when vectorized with 3
kernels:

for (i ...)
   r += a[i] * 3;
for (i ...)
  m1[i] = m1[i] * 3; // This matches the test case in avx1.ll
and a matrix multiply.

In each case the vectorized version was considerably slower.

radar://13304919

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02 04:02:52 +00:00
Michael Liao
a6b20ced76 Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
  but TLI.getShiftAmountTy() so far only return scalar type. As a
  result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
  TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
  return target-specificed scalar type or the same vector type as the
  1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
  type.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 18:40:30 +00:00
Duncan Sands
4d9b7c234f GCC thinks that this variable might be used uninitialized (it isn't).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176341 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 09:46:03 +00:00
Yiannis Tsiouris
2d1035def1 Re-format comments (and check commit access)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176270 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-28 16:59:10 +00:00
Nadav Rotem
f8b80de1a9 Revert r176166 because it broke one of the lit tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176171 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-27 05:56:20 +00:00
Nadav Rotem
e7c52282dd std::string to StringRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176166 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-27 05:23:56 +00:00
Chad Rosier
fe88aa0d14 [fast-isel] Make sure the FastLowerArguments function checks to make sure the
arguments type is a simple type.
rdar://13290455

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-26 01:05:31 +00:00
Michael Liao
d09318f901 Refine fix to PR10499, no functionality change
- Put expensive checking after simple one



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176060 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-25 23:16:36 +00:00
Michael Liao
5e6e15caa7 Fix PR10499
- Check whether SSE is available before lowering all 1s vector building with
  PCMPEQD, which is only available from SSE2



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176058 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-25 23:01:03 +00:00
Chad Rosier
fd3417d288 [fast-isel] Add X86FastIsel::FastLowerArguments to handle functions with 6 or
fewer scalar integer (i32 or i64) arguments. It completely eliminates the need
for SDISel for trivial functions.

Also, add the new llc -fast-isel-abort-args option, which is similar to
-fast-isel-abort option, but for formal argument lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176052 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-25 21:59:35 +00:00
Chad Rosier
dca83187b7 [ms-inline asm] Add support for the pushad/popad mnemonics.
rdar://13254235

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176036 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-25 19:06:27 +00:00
Nadav Rotem
f8db4478f8 Revert r169638 because it broke Mesa llvmpipe tests.
Fix PR15239.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-24 07:09:35 +00:00
Benjamin Kramer
36bd16ef0b X86: Disable cmov-memory patterns on subtargets without cmov.
Fixes PR15115.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175962 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-23 10:40:58 +00:00
Peter Collingbourne
c4952bfc31 x86_64: designate most general purpose and SSE registers as callee save under coldcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175911 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-22 19:19:44 +00:00
Eli Bendersky
700ed80d3d Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21 20:05:00 +00:00
Eli Bendersky
8389f24a66 getX86SubSuperRegister has a special mode with High=true for i64 which
exists solely to enable it to call itself for i8 with some registers.
The proposed patch simplifies the function somewhat to make the High
bit only meaningful for the i8 mode, which makes sense. No functional
difference (getX86SubSuperRegister is not getting called from anywhere
outside with i64 and High=true).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175762 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21 16:40:18 +00:00
Jim Grosbach
cb2ae3d98e MCParser: Update method names per coding guidelines.
s/AddDirectiveHandler/addDirectiveHandler/
s/ParseMSInlineAsm/parseMSInlineAsm/
s/ParseIdentifier/parseIdentifier/
s/ParseStringToEndOfStatement/parseStringToEndOfStatement/
s/ParseEscapedString/parseEscapedString/
s/EatToEndOfStatement/eatToEndOfStatement/
s/ParseExpression/parseExpression/
s/ParseParenExpression/parseParenExpression/
s/ParseAbsoluteExpression/parseAbsoluteExpression/
s/CheckForValidSection/checkForValidSection/

http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175675 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20 22:21:35 +00:00
Jim Grosbach
3450f800aa Update TargetLowering ivars for name policy.
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly

ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20 21:13:59 +00:00
Chad Rosier
9b5b8b0b94 [ms-inline asm] Make the comment a bit more verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20 18:03:44 +00:00
Elena Demikhovsky
52981c4b60 I optimized the following patterns:
sext <4 x i1> to <4 x i64>
 sext <4 x i8> to <4 x i64>
 sext <4 x i16> to <4 x i64>
 
I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns:
 (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
 
 The sext_in_reg (v4i32 x) may be lowered to shl+sar operations.
 The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution.

I also added a cost of this operations to the AVX costs table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175619 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20 12:42:54 +00:00
Chad Rosier
b86f1e5e55 [ms-inline asm] Force the use of a base pointer if the MachineFunction includes
MS-style inline assembly.

This is a follow-on to r175334.  Forcing a FP to be emitted doesn't ensure it
will be used.  Therefore, force the base pointer as well.  We now treat MS
inline assembly in the same way we treat functions with dynamic stack
realignment and VLAs.  This guarantees the BP will be used to reference 
parameters and locals.
rdar://13218191

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175576 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 23:50:45 +00:00
Jakub Staszak
608e355484 Add obvious constantness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175560 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 21:54:59 +00:00
Benjamin Kramer
b1e1d5d4a5 Clean up HiPE prologue emission a bit and avoid signed arithmetic tricks.
No intended functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175536 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 17:32:57 +00:00
Rafael Espindola
e5a83d15b2 Move LLVM_LIBRARY_VISIBILITY for consistency with what was done to
PPCJITInfo.cpp in r175394.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175531 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 17:14:33 +00:00
Eli Bendersky
faec9a3396 Make pass name more precise and fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 16:38:32 +00:00
Craig Topper
ff3139fe53 Fix capitalization in comment to match function name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175497 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 07:43:59 +00:00
Jakub Staszak
56f58ad0e4 Use array_pod_sort instead of std::sort.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 23:18:22 +00:00
NAKAMURA Takumi
9d7c53af30 X86FrameLowering.cpp: Fixup. Sorry for the breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175467 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 23:15:21 +00:00
NAKAMURA Takumi
82f7815e6f X86FrameLowering.cpp: Fix a warning in -Asserts. [-Wunused-variable]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175464 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 23:08:49 +00:00
Chad Rosier
20ea2bc391 Remove a useless assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175463 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 22:20:16 +00:00
Benjamin Kramer
6228999d82 Fix a 32/64 bit incompatibility in the HiPE prologue generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175458 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 21:45:01 +00:00
Benjamin Kramer
98fbe27ac8 Support for HiPE-compatible code emission, patch by Yiannis Tsiouris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 20:55:12 +00:00
Benjamin Kramer
774ec7ba05 X86: Add a note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175408 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 23:34:14 +00:00
Jakub Staszak
d61932bf84 Return false instead of 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175402 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 18:35:25 +00:00
NAKAMURA Takumi
3d6417d170 [msvc x64] Update X86CompilationCallback_Win64.asm corresponding to r175267.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175363 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 16:04:29 +00:00
Jakub Staszak
30fcfc39e2 Minor cleanups. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175359 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 13:34:26 +00:00
Bill Wendling
901d80065c Reinitialize the ivars in the subtarget so that they can be reset with the new features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175336 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 01:36:26 +00:00
Chad Rosier
b56606274d [ms-inline asm] Do not omit the frame pointer if we have ms-inline assembly.
If the frame pointer is omitted, and any stack changes occur in the inline
assembly, e.g.: "pusha", then any C local variable or C argument references
will be incorrect.  

I pass no judgement on anyone who would do such a thing. ;)
rdar://13218191

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 01:25:28 +00:00
Bill Wendling
ba6867d0ce Temporary revert of 175320.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175322 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 23:22:32 +00:00
Bill Wendling
9be8b4fc92 Reinitialize the ivars in the subtarget.
When we're recalculating the feature set of the subtarget, we need to have the
ivars in their initial state.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175320 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 23:18:01 +00:00
Bill Wendling
789cb5df9c Use the 'target-features' and 'target-cpu' attributes to reset the subtarget features.
If two functions require different features (e.g., `-mno-sse' vs. `-msse') then
we want to honor that, especially during LTO. We can do that by resetting the
subtarget's features depending upon the 'target-feature' attribute.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175314 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 22:31:27 +00:00
Chad Rosier
4fb25b7d79 [ms-inline asm] Adjust the EndLoc to account for the ']'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 21:58:13 +00:00
Rafael Espindola
8a8a2dcae0 Give these callbacks hidden visibility. It is better to not export them more
than we need to and some ELF linkers complain about directly accessing symbols
with default visibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 14:15:59 +00:00
Rafael Espindola
9fa05f98e0 Don't make assumptions about the mangling of static functions in extern "C"
blocks. We still don't have consensus if we should try to change clang or
the standard, but llvm should work with compilers that implement the current
standard and mangle those functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 14:08:43 +00:00
Benjamin Kramer
74b3c8da48 Make helpers static. Add missing include so LLVMInitializeObjCARCOpts gets C linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175264 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 12:30:38 +00:00
Eli Bendersky
d6f19c7163 The operand listing is very much outdated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 23:17:03 +00:00
Jakub Staszak
fe9b5a4f74 Simplify code. Remove "else after return".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175212 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 21:50:09 +00:00
Kay Tiong Khoo
7b672ed380 added basic support for Intel ADX instructions
-feature flag, instructions definitions, test cases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175196 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 19:08:21 +00:00
Nadav Rotem
b39a552949 80-col
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175189 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 18:20:48 +00:00
Elena Demikhovsky
60b3e18d67 Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).
Added a test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 08:20:26 +00:00
Rafael Espindola
bf7ac42663 Revert r175120 and r175121. Clang is producing the expected asm names again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175133 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 03:33:34 +00:00
Rafael Espindola
ad236eb8c6 Don't assume the mangling of static functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175121 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 02:49:18 +00:00
Nick Lewycky
48aaf5fd02 Don't build tail calls to functions with three inreg arguments on x86-32 PIC.
Fixes PR15250!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175092 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 21:59:15 +00:00
Chad Rosier
7b0bc3fe3e [ms-inline-asm] Add support for memory references that have non-immediate
displacements.
rdar://12974533


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 21:33:44 +00:00
Benjamin Kramer
f09e02f01a X86: Disable generation of rep;movsl when %esi is used as a base pointer.
This happens when there is both stack realignment and a dynamic alloca in the
function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the
base pointer and the next register spill will write into oblivion.

Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas
and freebsd a 4 byte stack alignment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175057 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 13:40:35 +00:00
Elena Demikhovsky
d29804f80d Prevent insertion of "vzeroupper" before call that preserves YMM registers, since a caller uses preserved registers across the call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175043 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 08:02:04 +00:00
Eric Christopher
23571f4f2c Check i1 as well as i8 variables for 8 bit registers for x86 inline
assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175036 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 06:01:05 +00:00
Kay Tiong Khoo
6c3daabc3e Added 0x0D to 2-byte opcode extension table for prefetch* variants
Fixed decode of existing 3dNow prefetchw instruction
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174920 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 00:19:12 +00:00
Kay Tiong Khoo
86494d7991 *fixed disassembly of some i386 system insts with intel syntax
*added file for test cases for i386 intel syntax

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174900 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11 19:46:36 +00:00
Eli Bendersky
16221a60a0 This is a follow-up on r174446, now taking Atom processors into
account. Atoms use LEA for updating SP in prologs/epilogs, and the
exact LEA opcode depends on the data model.

Also reapplying the test case which was added and then reverted
(because of Atom failures), this time specifying explicitly the CPU in
addition to the triple. The test case now checks all variations (data
mode, cpu Atom vs. Core).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174542 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06 20:43:57 +00:00
Eli Bendersky
2a1b60d791 Make sure the correct opcodes are used to SUB and ADD the stack
pointer in function prologs/epilogs. The opcodes should depend on the
data model (LP64 vs. ILP32) rather than the architecture bit-ness.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 21:53:29 +00:00
Jakob Stoklund Olesen
c3afc760e1 Move MRI liveouts to X86 return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174402 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 17:59:48 +00:00
Eli Bendersky
d07c2a5fa1 Fix comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 16:53:11 +00:00
Benjamin Kramer
a220aeb58f X86: Open up some opportunities for constant folding by postponing shift lowering.
Fixes PR15141.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04 15:19:33 +00:00
Benjamin Kramer
9fa9251bba X86: Simplify code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174326 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04 15:19:25 +00:00
Evgeniy Stepanov
9c02a27604 More MSan/ASan annotations.
This change lets us bootstrap LLVM/Clang under ASan and MSan. It contains
fixes for 2 issues:

- X86JIT reads return address from stack, which MSan does not know is
  initialized.
- bugpoint tests run binaries with RLIMIT_AS. This does not work with certain
  Sanitizers.

We are no longer including config.h in Compiler.h with this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174306 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04 07:03:24 +00:00
David Sehr
693c37aa86 Two changes relevant to LEA and x32:
1) allows the use of RIP-relative addressing in 32-bit LEA instructions under
   x86-64 (ILP32 and LP64)
2) separates the size of address registers in 64-bit LEA instructions from
   control by ILP32/LP64.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174208 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01 19:28:09 +00:00
Chad Rosier
108fb3202a [PEI] Pass the frame index operand number to the eliminateFrameIndex function.
Each target implementation was needlessly recomputing the index.
Part of rdar://13076458

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31 20:02:54 +00:00
Eric Christopher
e187e25996 Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31 00:50:48 +00:00
Eric Christopher
a9bd4b4647 Check and allow floating point registers to select the size of the
register for inline asm. This conforms to how gcc allows for effective
casting of inputs into gprs (fprs is already handled).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174008 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31 00:50:46 +00:00
Evan Cheng
a66f40a8cc Restrict sin/cos optimization to 64-bit only for now. 32-bit is a bit messy and less critical.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30 22:56:35 +00:00
Evan Cheng
9b5a14d59d Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173812 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29 18:08:22 +00:00
Hans Wennborg
7c1ac76769 Fix typo in X86BaseInfo.h that I introduced in r157818.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29 14:05:57 +00:00
Craig Topper
e6482fabd2 Merge SSE and AVX shuffle instructions in the comment printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29 07:54:31 +00:00
Evan Cheng
8688a58c53 Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
   the target provides a sincos library call.

Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.

rdar://13087969
PR13204


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29 02:32:37 +00:00
Craig Topper
467016e58d Fix 256-bit PALIGNR comment decoding to understand that it works on independent 256-bit lanes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173674 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28 07:41:18 +00:00
Craig Topper
53597b2c5c Add missing break in 256-bit palignr comment printing. No test case yet because the comment itself is still wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173669 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28 07:19:11 +00:00
Craig Topper
4aee1bb222 Fix inconsistent usage of PALIGN and PALIGNR when referring to the same instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28 06:48:25 +00:00
Benjamin Kramer
200b306f20 X86: Decode PALIGN operands so I don't have to do it in my head.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173572 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-26 13:31:37 +00:00
Benjamin Kramer
11f2bf7f15 X86: Do splat promotion later, so the optimizer can chew on it first.
This catches many cases where we can emit a more efficient shuffle for a
specific mask or when the mask contains undefs. Once the splat is lowered to
unpacks we can't do that anymore.

There is a possibility of moving the promotion after pshufb matching, but I'm
not sure if pshufb with a mask loaded from memory is faster than 3 shuffles, so
I avoided that for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-26 11:44:21 +00:00
Eli Bendersky
a5597f0eaf In this patch, we teach X86_64TargetMachine that it has a ILP32
(defined by the x32 ABI) mode, in which case its pointers are 32-bits
in size. This knowledge is also added to X86RegisterInfo that now
returns the appropriate registers in getPointerRegClass.

There are many outcomes to this change. In order to keep the patches
separate and manageable, we start by focusing on some simple testable
cases. The patch adds a test with passing a pointer to a function -
focusing on the difference between the two data models for x86-64.
Another test is added for handling of 'sret' arguments (and
functionality is added in X86ISelLowering to make it work).

A note on naming: the "x32 ABI" document refers to the AMD64
architecture (in LLVM it's distinguished by being is64Bits() in the
x86 subtarget) with two variations: the LP64 (default) data model, and
the ILP32 data model. This patch adds predicates to the subtarget
which are consistent with this naming scheme.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173503 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 22:07:43 +00:00
Renato Golin
b3755e7fa2 Moving Cost Tables up to share with other targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173382 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-24 23:01:00 +00:00
Michael Liao
13d08bf415 Fix an issue of pseudo atomic instruction DAG schedule
- Add list of physical registers clobbered in pseudo atomic insts
  Physical registers are clobbered when pseudo atomic instructions are
  expanded. Add them in clobber list to prevent DAG scheduler to
  mis-schedule them after these insns are declared side-effect free.
- Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173200 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22 21:47:38 +00:00
Benjamin Kramer
341c5fbe84 X86: Make sure we account for the FMA4 register immediate value, otherwise rip-rel relocations will be off by one byte.
PR15040.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22 18:05:59 +00:00
Eli Bendersky
9dd2a3b1f2 Initial patch for x32 ABI support.
Add the x32 environment kind to the triple, and separate the concept of
pointer size and callee save stack slot size, since they're not equal
on x32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173175 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22 18:02:49 +00:00
Tim Northover
0a29cb0454 Make APFloat constructor require explicit semantics.
Previously we tried to infer it from the bit width size, with an added
IsIEEE argument for the PPC/IEEE 128-bit case, which had a default
value. This default value allowed bugs to creep in, where it was
inappropriate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22 09:46:31 +00:00
Craig Topper
04f74a149d Use <0 checks in place of ==-1 because it results in simpler code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173010 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21 07:25:16 +00:00
Craig Topper
bbf9d3e493 Use MVT instead of EVT in LowerVECTOR_SHUFFLEtoBlend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21 07:19:54 +00:00
Craig Topper
9b33ef7c67 Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173008 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21 06:57:59 +00:00
Craig Topper
b99bafe36d Fix some 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21 06:21:54 +00:00
Craig Topper
b84b423634 Make helper method static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173005 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21 06:13:28 +00:00
Craig Topper
a080daf5c6 Convert more EVT's to MVT's in the lowering methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172995 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 21:50:27 +00:00
Craig Topper
d713c0f7f1 Capitalize lowerTRUNCATE so that it matches the other lower functions in this file despite it not matching coding standards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172994 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 21:34:37 +00:00
Renato Golin
053a211983 Revert CostTable algorithm, will re-write
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172992 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 20:57:20 +00:00
Craig Topper
26827f3dc5 Make LowerVSETCC a static function and use MVT instead of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172969 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 09:02:22 +00:00
Nadav Rotem
0c8607ba6a Revert 172708.
The optimization handles esoteric cases but adds a lot of complexity both to the X86 backend and to other backends.
This optimization disables an important canonicalization of chains of SEXT nodes and makes SEXT and ZEXT asymmetrical.
Disabling the canonicalization of consecutive SEXT nodes into a single node disables other DAG optimizations that assume
that there is only one SEXT node. The AVX mask optimizations is one example. Additionally this optimization does not update the cost model.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172968 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 08:35:56 +00:00