Jakob Stoklund Olesen
d93969c32a
Add an OtherPreserved field to the CalleeSaved TableGen class.
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This field specifies registers that are preserved across function calls,
but that should not be included in the generates SaveList array.
This can be used ot generate regmasks for architectures that save
registers through other means, like SPARC's register windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189084 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 02:25:47 +00:00
Venkatraman Govindaraju
e3b29fbc5f
[Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188738 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 01:26:14 +00:00
Venkatraman Govindaraju
d8de58e24c
[Sparc] Enable xword directive in sparcv9.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-10 20:13:20 +00:00
NAKAMURA Takumi
8e1d64666f
Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen.
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Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 06:38:37 +00:00
Venkatraman Govindaraju
8717679c44
[Sparc] Rewrite MBB's live-in registers for leaf functions. Also, add
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register i7 as a live-in if current function's return address is taken.
This revision fixes PR16269.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187433 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 19:53:10 +00:00
Venkatraman Govindaraju
80cdaf35ab
[Sparc] Use call's debugloc for the unimp instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187402 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 02:26:29 +00:00
Craig Topper
a0ec3f9b7b
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-14 04:42:23 +00:00
Venkatraman Govindaraju
eb4a55c949
[Sparc]: Add memory operands for the frame references in the storeRegToStackSlot
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and loadRegFromStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184935 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-26 12:40:16 +00:00
Chad Rosier
5b3fca50a0
The getRegForInlineAsmConstraint function should only accept MVT value types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-22 18:37:38 +00:00
Bill Wendling
ba54bca472
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 21:36:55 +00:00
David Blaikie
0187e7a9ba
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
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Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-16 20:34:27 +00:00
Venkatraman Govindaraju
1799921672
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183613 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 15:32:59 +00:00
Jakob Stoklund Olesen
ec2aaad01b
Remember the anyext patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183589 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 22:59:29 +00:00
Jakob Stoklund Olesen
7de1d327f1
Add missing zextloadi1 to i64 patterns. PR16721.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183587 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 22:55:05 +00:00
Bill Wendling
c1dcb8d654
Don't cache the instruction and register info from the TargetMachine, because
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the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183565 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:35:25 +00:00
Roman Divacky
6ca5fd3f30
Fix a typo in asm string of BP* family of instructions. With this fix
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I am able to compile/assemble/link/run /bin/echo from FreeBSD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183537 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 17:46:57 +00:00
Venkatraman Govindaraju
01021a8b93
[Sparc]: Use cmp instruction instead of subcc to compare integers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183463 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 00:03:36 +00:00
Bill Wendling
6a2e7ac0b6
Cache the TargetLowering info object as a pointer.
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Caching it as a pointer allows us to reset it if the TargetMachine object
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 00:43:09 +00:00
Venkatraman Govindaraju
1e06bcbd63
Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183243 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 18:33:25 +00:00
Venkatraman Govindaraju
e7cbb792c9
Sparc: Add support for indirect branch and blockaddress in Sparc backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 05:58:33 +00:00
Venkatraman Govindaraju
85cc972a06
Sparc: When storing 0, use %g0 directly in the store instruction instead of
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using two instructions (sethi and store).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 00:21:54 +00:00
Venkatraman Govindaraju
65ca7aa57d
Sparc: Combine add/or/sethi instruction with restore if possible.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183088 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-02 21:48:17 +00:00
Venkatraman Govindaraju
dd48226b15
Sparc: Perform leaf procedure optimization by default
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-02 02:24:27 +00:00
Venkatraman Govindaraju
a0b34d6c4a
Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics as non-leaf functions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183079 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 20:42:48 +00:00
Venkatraman Govindaraju
72ad17c48c
[Sparc] Generate correct code for leaf functions with stack objects
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 04:51:18 +00:00
Ahmed Bougacha
23ed37a6b7
Make SubRegIndex size mandatory, following r183020.
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This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 23:45:26 +00:00
Andrew Trick
6e0b2a0cb0
Order CALLSEQ_START and CALLSEQ_END nodes.
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Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29 22:03:55 +00:00
NAKAMURA Takumi
d1c180e030
SparcFrameLowering.cpp: Mark verifyLeafProcRegUse() as UNUSED. [-Wunused-function]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182850 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29 12:10:42 +00:00
Venkatraman Govindaraju
5300869256
[Sparc] Add support for leaf functions in sparc backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182822 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29 04:46:31 +00:00
Andrew Trick
ac6d9bec67
Track IR ordering of SelectionDAG nodes 2/4.
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Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-25 02:42:55 +00:00
Jakob Stoklund Olesen
89f530ebbf
Also expand 64-bit bitcasts.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 01:01:43 +00:00
Jakob Stoklund Olesen
5e5b78ca36
Implement spill and fill of I64Regs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 00:53:25 +00:00
Jakob Stoklund Olesen
900622e099
Mark i64 SETCC as expand so it is turned into a SELECT_CC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 00:28:36 +00:00
Jakob Stoklund Olesen
634123e98d
Don't use %g0 to materialize 0 directly.
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The wired physreg doesn't work on tied operands like on MOVXCC.
Add a README note to fix this later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182225 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 21:47:13 +00:00
Jakob Stoklund Olesen
60abcb786e
Select i64 values with %icc conditions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 20:38:21 +00:00
Jakob Stoklund Olesen
51d46c36bc
Add floating point selects on %xcc predicates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 20:33:11 +00:00
Jakob Stoklund Olesen
89db6732fb
Implement SPselectfcc for i64 operands.
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Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 20:20:54 +00:00
Venkatraman Govindaraju
21886a495a
[Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers.
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Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182219 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 20:07:20 +00:00
Jakob Stoklund Olesen
00ce0f6512
Handle i64 FrameIndex nodes in SPARC v9 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182216 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 19:14:24 +00:00
Venkatraman Govindaraju
a65d33760b
[Sparc] Implements hasReservedCallFrame and hasFP.
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This is to generate correct framesetup code when the function
has variable sized allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182108 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 15:14:34 +00:00
Venkatraman Govindaraju
d6b4caf291
[Sparc] Prevent instructions that defines or uses %o7 to be in call's delay slot.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182063 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 23:53:29 +00:00
Rafael Espindola
4a971705bc
Remove the MachineMove class.
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It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.
I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 01:16:13 +00:00
Rafael Espindola
6e53180db1
Remove unused argument.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 18:16:59 +00:00
Jakob Stoklund Olesen
ddb14ce76c
Passing arguments to varags functions under the SPARC v9 ABI.
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Arguments after the fixed arguments never use the floating point
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-21 21:36:49 +00:00
Jakob Stoklund Olesen
2c6b5a8d33
Fix the SETHIimm pattern for 64-bit code.
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Don't ignore the high 32 bits of the immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-21 21:18:03 +00:00
Jakob Stoklund Olesen
da8768b2dd
Compile varargs functions for SPARCv9.
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With a little help from the frontend, it looks like the standard va_*
intrinsics can do the job.
Also clean up an old bitcast hack in LowerVAARG that dealt with
unaligned double loads. Load SDNodes can specify an alignment now.
Still missing: Calling varargs functions with float arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179961 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20 22:49:16 +00:00
Tim Northover
6265d5c91a
Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20 12:32:17 +00:00
Jakob Stoklund Olesen
ad36608499
Add 64-bit multiply and divide instructions for SPARC v9.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179582 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16 02:57:02 +00:00
Jakob Stoklund Olesen
d9f88da7b3
Use i32 for all SPARC shift amounts, even in 64-bit mode.
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Test case by llvm-stress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179477 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 05:48:50 +00:00
Jakob Stoklund Olesen
618eda7a60
Add support for the abs64 SPARC v9 code model.
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For when 16 TB just isn't enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179474 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 05:10:36 +00:00