7 Commits

Author	SHA1	Message	Date
Dan Gohman	36a0947820	Eliminate more uses of llvm-as and llvm-dis. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8	2009-09-08 23:54:48 +00:00
Dan Gohman	7a01d0e971	Add explicit -march=x86 to these tests so that they don't ... default to -march=x86-64 on 64-bit hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63579 91177308-0d34-0410-b5e6-96231b3b80d8	2009-02-03 00:20:22 +00:00
Dan Gohman	e5af2d3a22	Make x86's BT instruction matching more thorough, and add some ... dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63266 91177308-0d34-0410-b5e6-96231b3b80d8	2009-01-29 01:59:02 +00:00
Dan Gohman	f31408d75c	Disable the register+memory forms of the bt instructions for now. Thanks ... to Eli for pointing out that these forms don't ignore the high bits of their index operands, and as such are not immediately suitable for use by isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62194 91177308-0d34-0410-b5e6-96231b3b80d8	2009-01-13 23:23:30 +00:00
Evan Cheng	ccb6976a69	Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61557 91177308-0d34-0410-b5e6-96231b3b80d8	2009-01-02 05:35:45 +00:00
Chris Lattner	1323e8bf6a	add PR # ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61427 91177308-0d34-0410-b5e6-96231b3b80d8	2008-12-25 05:40:38 +00:00
Chris Lattner	e55484eb45	Add a simple pattern for matching 'bt'. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61426 91177308-0d34-0410-b5e6-96231b3b80d8	2008-12-25 05:34:37 +00:00