Commit Graph

64 Commits

Author SHA1 Message Date
Evan Cheng
0f040a258f - Add "Bitcast" target instruction property for instructions which perform
nothing more than a bitcast.
- Teach tablegen to automatically infer "Bitcast" property.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 05:09:26 +00:00
Bob Wilson
a49c7dfb36 Improve the AsmMatcher's ability to handle suboperands.
When an operand class is defined with MIOperandInfo set to a list of
suboperands, the AsmMatcher has so far required that operand to also define
a custom ParserMatchClass, and InstAlias patterns have not been able to
set the individual suboperands separately.  This patch removes both of those
restrictions.  If a "compound" operand does not override the default
ParserMatchClass, then the AsmMatcher will now parse its suboperands
separately.  If an InstAlias operand has the same class as the corresponding
compound operand, then it will be handled as before; but if that check fails,
TableGen will now try to match up a sequence of InstAlias operands with the
corresponding suboperands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124314 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26 19:44:55 +00:00
NAKAMURA Takumi
36c3bc431b TableGen: PointerLikeRegClass can be accepted to operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124271 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26 02:03:48 +00:00
NAKAMURA Takumi
e5fffe9c3f Fix whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124270 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26 02:03:37 +00:00
Bob Wilson
55931ab992 Move InstAlias check of argument types to a separate loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123934 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20 18:38:10 +00:00
Bob Wilson
47c90a70ba Fix broken check for InstAlias argument used with different types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123932 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20 18:38:05 +00:00
Bob Wilson
5e8f2a65ca Precompute InstAlias operand mapping to result instruction operand indices.
There should be no functional change from this, but I think it's simpler this
way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123931 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20 18:38:02 +00:00
Bob Wilson
dc1a2bd3aa Fix some tablegen issues to allow using zero_reg for InstAlias definitions.
This is needed to allow an InstAlias for an instruction with an "OptionalDef"
result register (like ARM's cc_out) where you want to set the optional register
to reg0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123490 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-14 22:58:09 +00:00
Evan Cheng
c4af4638df Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17 20:13:28 +00:00
Chris Lattner
2ac190238e add fields to the .td files unconditionally, simplifying tblgen a bit.
Switch the ARM backend to use 'let' instead of 'set' with this change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 05:19:05 +00:00
Chris Lattner
90fd797dc7 add (and document) the ability for alias results to have
fixed physical registers.  Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118352 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 19:57:21 +00:00
Chris Lattner
98c870f87b generalize alias support to allow the result of an alias to
add fixed immediate values.  Move the aad and aam aliases to
use this, and document it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 19:25:43 +00:00
Chris Lattner
5bde734598 fix a bug where we had an implicit assumption that the
result instruction operand numbering matched the result pattern.

Fixing this allows us to move the xchg/test aliases to the .td file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 08:20:59 +00:00
Chris Lattner
414098571b fix some bugs in the alias support, unblocking changing of "clr" aliases
from c++ hacks to proper .td InstAlias definitions.  Change them!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118330 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:31:43 +00:00
Chris Lattner
662e5a30e8 Reimplement BuildResultOperands to be in terms of the result instruction's
operand list instead of the operand list redundantly declared on the alias
or instruction.

With this change, we finally remove the ins/outs list on the alias.  Before:
  def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
                  "movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
  def : InstAlias<"movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;

This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118329 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:14:44 +00:00
Chris Lattner
3f2c8e474b implement more checking to reject things like:
(someinst GR16:$foo, GR32:$foo)

Reimplement BuildAliasOperandReference to be correctly
based on the names of operands in the result pattern,
instead of on the instruction operand definitions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118328 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 07:06:09 +00:00
Chris Lattner
d0f225cafc decode and validate instruction alias result definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118327 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 06:54:38 +00:00
Chris Lattner
225549f775 disolve a hack, having CodeGenInstAlias decode the alias in the .td
file instead of the asmmatcher.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118324 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 06:39:47 +00:00
Chris Lattner
b501d4f673 Implement enough of the missing instalias support to get
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:34:34 +00:00
Chris Lattner
c76e80ded7 define a new CodeGenInstAlias. It has an asmstring and operand list for now,
todo: the result field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117894 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 04:05:41 +00:00
Chris Lattner
c240bb0ede factor the operand list (and related fields/operations) out of
CodeGenInstruction into its own helper class.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 04:03:32 +00:00
Chris Lattner
79b3cddfa2 avoid needless throw/catch/rethrow, stringref'ize some simple stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 03:19:09 +00:00
Chris Lattner
f780811456 eliminate the old InstFormatName which is always "AsmString",
simplify CodeGenInstruction. No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117891 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 02:15:23 +00:00
Chris Lattner
4d43d0fd99 move FlattenVariants out of AsmMatcherEmitter into a shared
CodeGenInstruction::FlattenAsmStringVariants method.  Use it
to simplify the code in AsmWriterInst, which now no longer 
needs to worry about variants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 01:07:14 +00:00
Jim Grosbach
5013f7469e Allow targets to optionally specify custom binary encoder functions for
operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 22:21:57 +00:00
Jim Grosbach
01855071e2 When figuring out which operands match which encoding fields in an instruction,
try to match them by name first. If there is no by-name match, fall back to
assuming they are in order (this was the previous behavior).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116211 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 18:25:51 +00:00
Owen Anderson
f523e476c2 Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:45:25 +00:00
Owen Anderson
5716180b1a Add an TargetInstrDesc bit to indicate that a given instruction is a conditional move.
Not intended functionality change, as nothing uses this yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114702 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 22:44:10 +00:00
Bill Wendling
73739d0bf1 Add back in r109901, which adds a Compare flag to the target instructions. It's
useful after all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-08 01:49:35 +00:00
Bill Wendling
5b55ff0c15 Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn't
need the Compare flag after all.

--- Reverse-merging r109901 into '.':
U    include/llvm/Target/TargetInstrDesc.h
U    include/llvm/Target/Target.td
U    utils/TableGen/InstrInfoEmitter.cpp
U    utils/TableGen/CodeGenInstruction.cpp
U    utils/TableGen/CodeGenInstruction.h



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110424 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06 01:36:09 +00:00
Bill Wendling
1844b1a5a4 Add a "Compare" flag to the target instruction descriptor. This will be used
later to identify and possibly remove superfluous compare instructions -- those
that are testing for and setting a status flag that should already be set.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 22:48:39 +00:00
Eric Christopher
1f4a1493fb Remove isTwoAddress from llvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106470 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 20:35:09 +00:00
Chris Lattner
9414ae5291 hoist some funky logic into CodeGenInstruction
from two places in CodeGenDAGPatterns.cpp, and
use it in DAGISelMatcherGen.cpp instead of using
an incorrect predicate that happened to get lucky
on our current targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 20:09:24 +00:00
Chris Lattner
f506b6b471 capture implicit uses and defs in CodeGenInstruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 21:42:03 +00:00
Chris Lattner
f55eed299b rewrite this to not artificially force concat the ins/outs list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98870 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 21:07:39 +00:00
Chris Lattner
b0be4d261b eliminate support for "ops" in the input/output list of an
instruction.  Instructions must use 'ins' and 'outs' now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98868 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:56:35 +00:00
Chris Lattner
cedef1ccf0 remove some code that was working around old sparc v9 backend bugs.
Add checking that the input/output operand list in spelled right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98865 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:50:52 +00:00
Dan Gohman
bc9d98b52d The mayHaveSideEffects flag is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-27 23:47:46 +00:00
Chris Lattner
a7d479c7bd Introduce a new CodeGenInstruction::ConstraintInfo class
for representing constraint info semantically instead of
as a c expression that will be blatted out to the .inc
file.  Fix X86RecognizableInstr to use this instead of
parsing C code :).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-10 01:45:28 +00:00
Benjamin Kramer
d4f195999a Reimplement getToken and SplitString as "StringRef helper functions"
- getToken is modeled after StringRef::split but it can split on multiple
  separator chars and skips leading seperators.
- SplitString is a StringRef::split variant for more than 2 elements with the
  same behaviour as getToken.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93161 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-11 18:03:24 +00:00
Jim Grosbach
06801722a4 Add @earlyclobber TableGen constraint
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91554 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16 19:43:02 +00:00
Jim Grosbach
f0a4fad995 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91442 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15 19:28:13 +00:00
Dan Gohman
533297b58d Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-29 18:10:34 +00:00
Evan Cheng
799d697bf8 Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When
set, these flags indicate the instructions source / def operands have special
register allocation requirement that are not captured in their register classes.
Post-allocation passes (e.g. post-alloc scheduler) should not change their
allocations. e.g. ARM::LDRD require the two definitions to be allocated
even / odd register pair.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83196 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 08:21:18 +00:00
Bob Wilson
fd87e6a7aa Fix bad length argument to substr calls. Apparently I'm the first one to
attempt more than 2 constraints on an instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80169 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-26 22:50:39 +00:00
David Greene
e8cf21e8e3 Make BinOps typed and require a type specifier for !nameconcat. This
allows binops to be used in typed contexts such as when passing
arguments to classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69921 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 21:25:15 +00:00
David Greene
c7cafcd815 Implement !nameconcat to concatenate strings and look up the resulting
name in the symbol table, returning an object.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69822 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-22 20:18:10 +00:00
Dan Gohman
15511cf166 Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03 18:15:48 +00:00
Matthijs Kooijman
677fbfa450 Remove redundant word in tblgen error message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58250 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-27 15:59:43 +00:00
Dale Johannesen
48c1bc2ace Handle some 64-bit atomics on x86-32, some of the time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56963 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-02 18:53:47 +00:00