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r233080 | marek.olsak | 2015-03-24 09:40:38 -0400 (Tue, 24 Mar 2015) | 4 lines
R600/SI: Insert more NOPs after READLANE on VI, don't use NOPs on CI
This is a candidate for stable.
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r233075 | marek.olsak | 2015-03-24 09:40:08 -0400 (Tue, 24 Mar 2015) | 8 lines
R600/SI: Expand fract to floor, then only select V_FRACT on CI
V_FRACT is buggy on SI.
R600-specific code is left intact.
v2: drop the multiclass, use complex VOP3 patterns
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r232957 | thomas.stellard | 2015-03-23 12:06:01 -0400 (Mon, 23 Mar 2015) | 5 lines
R600/SI: Fix crash in SIInstrInfo::areLoadsFromSameBasePtr()
This function assumed that SMRD instructions always have immediate
offsets, which is not always the case.
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r234975 | lhames | 2015-04-14 23:39:22 -0400 (Tue, 14 Apr 2015) | 5 lines
[RuntimeDyld] Make sure we emit MachO __eh_frame and __gcc_except_tab sections,
even if there are no references to them in the code.
This allows exceptions thrown from JIT'd code to be caught by the JIT itself.
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r233410 | ahmed.bougacha | 2015-03-27 16:35:49 -0400 (Fri, 27 Mar 2015) | 10 lines
[CodeGen] Don't attempt a tail-call with a non-forwarded explicit sret.
Tailcalls are only OK with forwarded sret pointers. With explicit sret,
one approximation is to check that the pointer isn't an Instruction, as
in that case it might point into some local memory (alloca). That's not
OK with tailcalls.
Explicit sret counterpart to r233409.
Differential Revison: http://reviews.llvm.org/D8510
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r233409 | ahmed.bougacha | 2015-03-27 16:28:30 -0400 (Fri, 27 Mar 2015) | 7 lines
[CodeGen] Don't attempt a tail-call with implicit sret.
Tailcalls are only OK with forwarded sret pointers. With sret demotion,
they're not, as we'd have a pointer into a soon-to-be-dead stack frame.
Differential Revison: http://reviews.llvm.org/D8510
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r232386 | thomas.stellard | 2015-03-16 11:53:55 -0400 (Mon, 16 Mar 2015) | 8 lines
R600/SI: don't try min3/max3/med3 with f64
There are no opcodes for this. This also adds a test case.
v2: make test more robust
Patch by: Grigori Goronzy
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r231659 | marek.olsak | 2015-03-09 11:48:09 -0400 (Mon, 09 Mar 2015) | 4 lines
R600/SI: Limit SGPRs to 80 on Tonga and Iceland
This is a candidate for stable.
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r229752 | marek.olsak | 2015-02-18 17:12:45 -0500 (Wed, 18 Feb 2015) | 10 lines
R600/SI: Fix READLANE and WRITELANE lane select for VI
VOP2 declares vsrc1, but VOP3 declares src1.
We can't use the same "ins" if the operands have different names in VOP2
and VOP3 encodings.
This fixes a hang in geometry shaders which spill M0 on VI.
(BTW it doesn't look like M0 needs spilling and the spilling seems
duplicated 3 times)
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r232943 | petarj | 2015-03-23 12:28:13 +0000 (Mon, 23 Mar 2015) | 10 lines
Fix sign extension for MIPS64 in makeLibCall function
Fixing sign extension in makeLibCall for MIPS64. In MIPS64 architecture all
32 bit arguments (int, unsigned int, float 32 (soft float)) must be sign
extended. This fixes test "MultiSource/Applications/oggenc/".
Patch by Strahinja Petrovic.
Differential Revision: http://reviews.llvm.org/D7791
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r228765 | petarj | 2015-02-10 23:30:14 +0000 (Tue, 10 Feb 2015) | 12 lines
Fix makeLibCall argument (signed) in SoftenFloatRes_XINT_TO_FP function
The isSigned argument of makeLibCall function was hard-coded to false
(unsigned). This caused zero extension on MIPS64 soft float.
As the result SingleSource/Benchmarks/Stanford/FloatMM test and
SingleSource/UnitTests/2005-07-17-INT-To-FP test failed.
The solution was to use the proper argument.
Patch by Strahinja Petrovic.
Differential Revision: http://reviews.llvm.org/D7292
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r231237 | vkalintiris | 2015-03-04 12:10:18 +0000 (Wed, 04 Mar 2015) | 6 lines
[mips] Specify the correct value type when combining a CMovFP node.
This commit fixes a bug introduced in r230956 where we were creating
CMovFP_{T,F} nodes with multiple return value types (one for each operand).
With this change the return value type of the new node is the same as the
value type of the True/False operands of the original node.
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r230956 | vkalintiris | 2015-03-02 12:47:32 +0000 (Mon, 02 Mar 2015) | 10 lines
[mips] Optimize conditional moves where RHS is zero.
Summary:
When the RHS of a conditional move node is zero, we can utilize the $zero
register by inverting the conditional move instruction and by swapping the
order of its True/False operands.
Reviewers: dsanders
Differential Revision: http://reviews.llvm.org/D7945
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r230500 | vmedic | 2015-02-25 15:24:37 +0000 (Wed, 25 Feb 2015) | 1 line
[MIPS]Multiple and add instructions for Mips are currently available in mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files.
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r232382 | petarj | 2015-03-16 15:01:09 +0000 (Mon, 16 Mar 2015) | 13 lines
[MIPS] Fix justify error for small structures
Fix justify error for small structures bigger than 32 bits in fixed
arguments for MIPS64 big endian. There was a problem when small structures
are passed as fixed arguments. The structures that are bigger than 32 bits
but smaller than 64 bits were not left justified properly on MIPS64 big
endian. This is fixed by shifting the value to make it left justified when
appropriate.
Patch by Aleksandar Beserminji.
Differential Revision: http://reviews.llvm.org/D8174
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r230742 | vkalintiris | 2015-02-27 09:01:39 +0000 (Fri, 27 Feb 2015) | 12 lines
[mips] Account for constant-zero operands in ADDE nodes.
Summary:
We identify the cases where the operand to an ADDE node is a constant
zero. In such cases, we can avoid generating an extra ADDu instruction
disguised as an identity move alias (ie. addu $r, $r, 0 --> move $r, $r).
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7906
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r230657 | petarj | 2015-02-26 18:35:15 +0000 (Thu, 26 Feb 2015) | 13 lines
Fix justify error for small structures in varargs for MIPS64BE
There was a problem when passing structures as variable arguments.
The structures smaller than 64 bit were not left justified on MIPS64
big endian. This is now fixed by shifting the value to make it left-
justified when appropriate.
This fixes the bug http://llvm.org/bugs/show_bug.cgi?id=21608
Patch by Aleksandar Beserminji.
Differential Revision: http://reviews.llvm.org/D7881
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r230235 | dsanders | 2015-02-23 17:22:16 +0000 (Mon, 23 Feb 2015) | 16 lines
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled.
Summary:
-mno-odd-spreg prohibits the use of odd-numbered single-precision floating
point registers. However, vector insert/extract was still using them when
manipulating the subregisters of an MSA register. Fixed this by ensuring
that insertion/extraction is only performed on even-numbered vector
registers when -mno-odd-spreg is given.
Reviewers: vmedic, sstankovic
Reviewed By: sstankovic
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7672
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r227430 | vmedic | 2015-01-29 11:33:41 +0000 (Thu, 29 Jan 2015) | 1 line
[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.
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r227084 | vmedic | 2015-01-26 10:33:43 +0000 (Mon, 26 Jan 2015) | 1 line
When disassembler meets compact jump instructions for r6 it crashes as the access to operands array is out of range. This patch removes dedicated decoder method that wrongly handles decoding of these instructions.
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r226905 | tomatabacu | 2015-01-23 10:40:19 +0000 (Fri, 23 Jan 2015) | 18 lines
[mips] Add new error message and improve testing for parsing the .module directive.
Summary:
We used to silently ignore any empty .module's and we used to give an error saying that we found
an "unexpected token at start of statement" when the value of the option wasn't an identifier (e.g. if it was a number).
We now give an error saying that we "expected .module option identifier" in both of those cases.
I also fixed the other tests in mips-abi-bad.s, which all seemed to be broken.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7095
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r226652 | vmedic | 2015-01-21 10:47:36 +0000 (Wed, 21 Jan 2015) | 1 line
[Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions.
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r226408 | dsanders | 2015-01-18 18:38:36 +0000 (Sun, 18 Jan 2015) | 9 lines
[mips] Make whitespace in disassembler tests more consistent. NFC.
The tests for the ISA's should now be approximately diffable. That is, the
output of 'diff valid-mips1.txt valid-mips2.txt' should be emit the lines
for instructions that were added/removed to/from MIPS-I by MIPS-II. This
doesn't work perfectly at the moment due to ordering differences but it
should be close.
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r226166 | vmedic | 2015-01-15 14:18:12 +0000 (Thu, 15 Jan 2015) | 1 line
Add disassembler tests for mips64r6 platform. There are no functional changes.
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r226165 | vmedic | 2015-01-15 14:11:38 +0000 (Thu, 15 Jan 2015) | 1 line
Add disassembler tests for mips32r6 platform. There are no functional changes.
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r226164 | vmedic | 2015-01-15 14:06:34 +0000 (Thu, 15 Jan 2015) | 1 line
Add disassembler tests for mips64r2 platform. There are no functional changes.
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r226151 | vmedic | 2015-01-15 08:50:20 +0000 (Thu, 15 Jan 2015) | 1 line
Add disassembler tests for mips64 platform. There are no functional changes.
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r229236 | Matthew.Arsenault | 2015-02-13 23:22:00 -0500 (Fri, 13 Feb 2015) | 7 lines
R600/SI: Fix implicit vcc operand to v_div_fmas_*
This should allow finally fixing the f64 fdiv implementation.
Test is disabled for VI since there seems to be a problem with one
of the buffer load instructions on it.
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r229230 | Matthew.Arsenault | 2015-02-13 22:40:35 -0500 (Fri, 13 Feb 2015) | 4 lines
R600/SI: Fix not encoding src2 for v_div_scale_{f32|f64}
This apparently got lost in the VI changes.
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Tom Stellard
Daniel Sanders