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40 Commits

Author SHA1 Message Date
Elena Demikhovsky
1c21f2ef8c AVX-512: Added intrinsics for ADDSS/D, MULSS/D, SUBSS/D, DIVSS/D 
instructions. These intrinsics are comming with rounding mode.
Added intrinsics for MAXSS/D, MINSS/D - with and without  sae.

By Asaf Badouh (asaf.badouh@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237560 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-18 07:24:19 +00:00
Elena Demikhovsky
8189eb4d7e AVX-512: Added SKX instructions and intrinsics: 
{add/sub/mul/div/} x {ps/pd} x {128/256} 2. max/min with sae

By Asaf Badouh (asaf.badouh@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236971 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-11 06:05:05 +00:00
Elena Demikhovsky
d08d0340e5 AVX-512: Added all forms of FP compare instructions for KNL and SKX. 
Added intrinsics for the instructions. CC parameter of the intrinsics was changed from i8 to i32 according to the spec.

By Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236714 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-07 11:24:42 +00:00
Elena Demikhovsky
70a6f4522a AVX-512: added integer "add" and "sub" instructions with saturation for SKX 
with intrinsics and tests

by Asaf Badouh (asaf.badouh@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236418 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-04 12:35:55 +00:00
Elena Demikhovsky
869807297d AVX-512: Added VPACK* instructions forms for KNL and SKX 
and their intrinsics
by Asaf Badouh (asaf.badouh@intel.com)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236414 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-04 09:14:02 +00:00
Sanjay Patel
f060668270 [x86] remove RCPPS and RSQRTPS intrinsic instruction definitions 
We don't need codegen-only intrinsic instructions for the vector forms of these instructions.

This makes the reciprocal estimate instruction lowering identical to how we handle normal
square roots: (V)SQRTPS / (V)SQRTPD.

No existing regression tests fail with this patch.

Differential Revision: http://reviews.llvm.org/D9301



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236013 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-28 18:48:45 +00:00
Elena Demikhovsky
44a0c9071a AVX-512: Added "pandn" intrinsics set 
by Asaf Badouh (asaf.badouh@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235971 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-28 08:12:42 +00:00
Sanjay Patel
95619d83af fix 80-cols; NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235902 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-27 17:45:44 +00:00
Sanjay Patel
4e9cdece79 fix typos; NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235896 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-27 17:03:31 +00:00
Elena Demikhovsky
a1fa0de258 AVX-512: Added logical and arithmetic instructions for SKX 
by Asaf Badouh (asaf.badouh@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235375 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-21 10:27:40 +00:00
Elena Demikhovsky
4eb165220f AVX-512: intrinsics for VPADD, VPMULDQ and VPSUB 
by Asaf Badouh (asaf.badouh@intel.com)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233906 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-02 10:51:40 +00:00
Elena Demikhovsky
f5f12f1e92 AVX-512: added intrinsics for VPAND, VPOR and VPXOR 
by Asaf Badouh (asaf.badouh@intel.com)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233525 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-30 08:30:34 +00:00
Quentin Colombet
be45e0e669 [X86] Fix a regression introduced by r223641. 
The permps and permd instructions have their operands swapped compared to the
intrinsic definition. Therefore, they do not fall into the INTR_TYPE_2OP
category.

I did not create a new category for those two, as they are the only one AFAICT
in that case.

<rdar://problem/20108262>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232085 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-12 19:34:12 +00:00
Elena Demikhovsky
fdafc8fd5e AVX-512: recommitted 229837 + bugfix + test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230223 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-23 15:12:31 +00:00
Eric Christopher
8c4bb575e1 Revert "AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics." 
The instructions were being generated on architectures that don't support avx512.

This reverts commit r229837.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229942 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-20 00:45:28 +00:00
Elena Demikhovsky
675d06d1d0 AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229837 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-19 10:48:04 +00:00
Elena Demikhovsky
87483ed180 AVX-512: Added support for FP instructions with embedded rounding mode. 
By Asaf Badouh <asaf.badouh@intel.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229645 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-18 07:59:20 +00:00
Elena Demikhovsky
b9d3801cd2 AVX-512: Added FMA intrinsics with rounding mode 
By Asaf Badouh and Elena Demikhovsky

Added special nodes for rounding: FMADD_RND, FMSUB_RND..
It will prevent merge between nodes with rounding and other standard nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227303 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-28 10:21:27 +00:00
Elena Demikhovsky
1a637e9fc0 AVX-512: Added FMA instructions, intrinsics an tests for KNL and SKX targets 
by Asaf Badouh

http://reviews.llvm.org/D6456



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224764 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 10:30:39 +00:00
Elena Demikhovsky
c1aa521fb4 AVX-512: Added all forms of BLENDM instructions, 
intrinsics, encoding tests for AVX-512F and skx instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224707 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-22 13:52:48 +00:00
Elena Demikhovsky
3f2027522c AVX-512: Added EXPAND instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224241 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-15 10:03:52 +00:00
Cameron McInally
14273ae2e4 [AVX512] Add support for 512b variable bit shift intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224028 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-11 17:13:05 +00:00
Elena Demikhovsky
11fb1d0eb5 AVX-512: Added all forms of COMPRESS instruction 
+ intrinsics + tests


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224019 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-11 15:02:24 +00:00
Elena Demikhovsky
c4fbd3fd62 X86 intrinsics moved form X86ISelLowering.cpp to X86IntrinsicsInfo.h 
X86ISelLowering.cpp has a long switch for intrinsics. I moved a part of
this long switch to the new intrinsics table in X86IntrinsicsInfo.h.
No functional changes, just code and compile time optimization.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223641 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-08 09:03:08 +00:00
Ahmed Bougacha
3b9ac8c7c3 [X86] Refactor PMOV[SZ]Xrm to add missing AVX2 patterns. 
Most patterns will go away once the extload legalization changes land.

Differential Revision: http://reviews.llvm.org/D6125


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223567 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-06 01:31:07 +00:00
Michael Liao
d3c452a506 [X86] Clean up whitespace as well as minor coding style 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223339 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-04 05:20:33 +00:00
Elena Demikhovsky
10c8f38047 AVX-512: Scalar ERI intrinsics 
including SAE mode and memory operand.
Added AVX512_maskable_scalar template, that should cover all scalar instructions in the future.

The main difference between AVX512_maskable_scalar<> and AVX512_maskable<> is using X86select instead of vselect.
I need it, because I can't create vselect node for MVT::i1 mask for scalar instruction.

http://reviews.llvm.org/D6378



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222820 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-26 10:46:49 +00:00
Cameron McInally
9f4bb0420d [AVX512] Add 512b integer shift by variable intrinsics and patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222786 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-25 20:41:51 +00:00
Cameron McInally
be30336912 [AVX512] Add integer shift by immediate intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221811 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-12 19:58:54 +00:00
Elena Demikhovsky
5f9c438577 AVX-512: Intrinsics for ERI 
3 instructions: vrcp28, vrsqrt28, vexp2, only vector forms.
Intrinsics include SAE (Suppres All Exceptions) parameter.

http://reviews.llvm.org/D6214



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221774 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-12 07:31:03 +00:00
Robert Khasanov
0e3754615e [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VPCMP/VPCMPU{BWDQ} 
Added CMP_MASK_CC intrinsic type.
Added tests for intrinsics.

Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219316 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-08 15:49:26 +00:00
Robert Khasanov
8acdc5232d [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VCMPGT{BWDQ}. 
Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218670 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-30 12:15:52 +00:00
Robert Khasanov
175ff01f0f [AVX512] Added intrinsics for 128- and 256-bit versions of VCMPEQ{BWDQ} 
Fixed lowering of this intrinsics in case when mask is v2i1 and v4i1.
Now cmp intrinsics lower in the following way:
 (i8 (int_x86_avx512_mask_pcmpeq_q_128
             (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
 (i8 (bitcast
   (v8i1 (insert_subvector undef,
           (v2i1 (and (PCMPEQM %a, %b),
                      (extract_subvector
                         (v8i1 (bitcast %mask)), 0))), 0))))


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218669 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-30 11:41:54 +00:00
Robert Khasanov
cfa5724d50 [AVX512] Added intrinsics for VPCMPEQB and VPCMPEQW. 
Added new operand type for intrinsics (IIT_V64)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218668 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-30 11:32:22 +00:00
Robert Khasanov
58da66b2bf [AVX512] Enabled intrinsics for VPCMPEQD and VPCMPEQQ. 
Added CMP_MASK intrinsic type


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218667 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-30 11:19:50 +00:00
Elena Demikhovsky
a91600713d Fixed compilation problem on Windows (initialization of non-aggregate type). 
After commit 217131.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217134 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-04 07:20:39 +00:00
Elena Demikhovsky
df1bc5a200 X86 Intrinsics table - changed to a static table sorted by intrinsic id. 
Used binary search over the tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217131 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-04 06:34:34 +00:00
Elena Demikhovsky
519ec3a914 X86 intrinsics table - simplifies intrinsics lowering. 
The tables are initialized when X86TargetLowering object is created.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216345 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-24 09:19:56 +00:00
Elena Demikhovsky
8b88009194 Reverted last commit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215827 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-17 09:36:07 +00:00
Elena Demikhovsky
a73ac1f463 Added a table for intrinsics on X86. 
It should remove dosens of lines in handling instrinsics (in a huge switch) and give an easy way to add new intrinsics.
I did not completed to move al intrnsics to the table, I'll do this in the upcomming commits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215826 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-17 09:00:20 +00:00