Commit Graph

19864 Commits

Author SHA1 Message Date
Tim Northover
e5a81a130f Stop putting operations after a tail call.
This prevents the emission of DAG-generated vreg definitions after a
tail call be dropping them entirely (on the grounds that nothing could
use them anyway, and they interfere with O0 CodeGen).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185754 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-06 12:58:45 +00:00
Nico Rieck
8064628379 MC: Implement COFF .linkonce directive
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185753 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-06 12:13:10 +00:00
David Majnemer
fa4133b1d1 InstCombine: typo in or_icmp_eq_B_0_icmp_ult_A_B test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185737 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-06 00:54:07 +00:00
Nick Lewycky
dc89737bcd Extend 'readonly' and 'readnone' to work on function arguments as well as
functions. Make the function attributes pass add it to known library functions
and when it can deduce it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185735 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-06 00:29:58 +00:00
Michael Gottesman
23fabedce5 [TRE] Combined another test into basic.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185729 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 22:24:06 +00:00
Michael Gottesman
cd56727b55 [TRE] Merged several tests into the the test basic.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185723 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 20:45:13 +00:00
Arnold Schwaighofer
fe3b2995aa ARM: Add a pack pattern for matching arithmetic shift right
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185714 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 18:57:49 +00:00
Arnold Schwaighofer
ffd3bb8f0d ARM: Fix incorrect pack pattern
A "pkhtb x, x, y asr #num" uses the lower 16 bits of "y asr #num" and packs them
in the bottom half of "x". An arithmetic and logic shift are only equivalent in
this context if the shift amount is 16. We would be shifting in ones into the
bottom 16bits instead of zeros if "y" is negative.

radar://14338767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185712 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 18:28:39 +00:00
Richard Sandiford
71804149a3 [SystemZ] Remove no-op MVCs
The stack coloring pass has code to delete stores and loads that become
trivially dead after coloring.  Extend it to cope with single instructions
that copy from one frame index to another.

The testcase happens to show an example of this kicking in at the moment.
It did occur in Real Code too though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 14:38:48 +00:00
Richard Sandiford
5f1c7e5eac Fix double renaming bug in stack coloring pass
The stack coloring pass renumbered frame indexes with a loop of the form:

  for each frame index FI
    for each instruction I that uses FI
      for each use of FI in I
        rename FI to FI'

This caused problems if an instruction used two frame indexes F0 and F1
and if F0 was renamed to F1 and F1 to F2.  The first time we visited the
instruction we changed F0 to F1, then we changed both F1s to F2.

In other words, the problem was that SSRefs recorded which instructions
used an FI, but not which MachineOperands and MachineMemOperands within
that instruction used it.

This is easily fixed for MachineOperands by walking the instructions
once and processing each operand in turn.  There's already a loop to
do that for dead store elimination, so it seemed more efficient to
fuse the two at the block level.

MachineMemOperands are more tricky because they can be shared between
instructions.  The patch handles them by making SSRefs an array of
MachineMemOperands rather than an array of MachineInstrs.  We might end
up processing the same MachineMemOperand twice, but that's OK because
we always know from the SSRefs index what the original frame index was.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 14:24:47 +00:00
Richard Sandiford
cf1b5bd60a [SystemZ] Enable the use of MVC for frame-to-frame spills
...now that the problem that prompted the restriction has been fixed.

The original spill-02.py was a compromise because at the time I couldn't
find an example that actually failed without the two scavenging slots.
The version included here did.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185701 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 14:02:01 +00:00
Ulrich Weigand
457571ed69 [PowerPC] Add some special @got@tprel fixup cases
When a target@got@tprel or target@got@tprel@l symbol variant is used in
a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail,
since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO
relocation types do not exist.

However, since such symbol variants resolve to GOT offsets which are
always 4-aligned, we can simply instead use the _DS variants of the
relocation types, which *do* exist.

The same applies for the @got@dtprel variants.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185700 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 13:49:46 +00:00
Richard Sandiford
47734db936 [SystemZ] Allocate a second register scavenging slot
This is another prerequisite for frame-to-frame MVC copies.
I'll commit the patch that makes use of the slot separately.

The downside of trying to test many corner cases with each of the
available addressing modes is that a fair few tests need to account
for the new frame layout.  I do still think it's useful to have all
these tests though, since it's something that wouldn't get much coverage
otherwise.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185698 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 13:11:52 +00:00
Rafael Espindola
61de142984 Don't create an archive if, for example, we are asked to print the index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185697 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 13:03:07 +00:00
Ulrich Weigand
3d4427347e [PowerPC] Make test case buildable with GNU as
The ppc64-fixups.s test currently fails to build with GNU as, since it
does not support plain symbols as arguments to li/lis.  Rewrite the test
for R_PPC64_ADDR16 and R_PPC64_REL16 to use lwz instead.

Allowing the test case to be built with both LLVM and GNU as makes it
easier to spot unwanted difference in the output.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185694 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 12:33:03 +00:00
Ulrich Weigand
23a72c8f7e [PowerPC] Support @tls in the asm parser
This adds support for the last missing construct to parse TLS-related
assembler code:
   add 3, 4, symbol@tls

The ADD8TLS currently hard-codes the @tls into the assembler string.
This cannot be handled by the asm parser, since @tls is parsed as
a symbol variant.  This patch changes ADD8TLS to have the @tls suffix
printed as symbol variant on output too, which allows us to remove
the isCodeGenOnly marker from ADD8TLS.  This in turn means that we
can add a AsmOperand to accept @tls marked symbols on input.

As a side effect, this means that the fixup_ppc_tlsreg fixup type
is no longer necessary and can be merged into fixup_ppc_nofixup.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 12:22:36 +00:00
Joey Gouly
00d9fe2de7 PR16490: fix a crash in ARMDAGToDAGISel::SelectInlineAsm.
In the SelectionDAG immediate operands to inline asm are constructed as
two separate operands. The first is a constant of value InlineAsm::Kind_Imm
and the second is a constant with the value of the immediate.

In ARMDAGToDAGISel::SelectInlineAsm, if we reach an operand of Kind_Imm we
should skip over the next operand too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185688 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 10:19:40 +00:00
David Majnemer
b1b738e036 InstCombine: (icmp eq B, 0) | (icmp ult A, B) -> (icmp ule A, B-1)
This transform allows us to turn IR that looks like:
  %1 = icmp eq i64 %b, 0
  %2 = icmp ult i64 %a, %b
  %3 = or i1 %1, %2
  ret i1 %3

into:
  %0 = add i64 %b, -1
  %1 = icmp uge i64 %0, %a
  ret i1 %1

which means we go from lowering:
        cmpq    %rsi, %rdi
        setb    %cl
        testq   %rsi, %rsi
        sete    %al
        orb     %cl, %al
        ret

to lowering:
        decq    %rsi
        cmpq    %rdi, %rsi
        setae   %al
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185677 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 00:31:17 +00:00
David Blaikie
09bb56f0a0 DebugInfo: Consider global variables without locations to be valid
We were being a bit too aggresive here in classifying global variables
with no global reference or constant value to be invalid - this would
cause LLVM to not emit the DWARF description of the global variable if
it had been optimized away, which isn't helpful for users who might
benefit from the global variable's description even if there's no
location information.

This also fixes a crasher issue here that I was unable to reduce a test
case for - involving a using decl (& subsequent
DW_TAG_imported_declaration ) of such a global variable that, once
optimized away, would crash when an attempt to emit the imported
declaration was made.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185675 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 23:15:18 +00:00
Nico Rieck
a6d343a688 MC: Add .section directive to COFF
Supports GAS flags "abdnrswxy". No support for alignment or subsections.

Fixes PR16366.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185669 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 21:32:07 +00:00
David Majnemer
e7006bb04b InstCombine: Reimplementation of visitUDivOperand
This transform was originally added in r185257 but later removed in
r185415.  The original transform would create instructions speculatively
and then discard them if the speculation was proved incorrect.  This has
been replaced with a scheme that splits the transform into two parts:
preflight and fold.  While we preflight, we build up fold actions that
inform the folding stage on how to act.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 21:17:49 +00:00
Rafael Espindola
6d88f9b73a Add support for archives with no symbol table or string table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185664 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 19:40:23 +00:00
Ulrich Weigand
972befb3f2 [PowerPC] Implement writeNopData
This implements a proper PPCAsmBackend::writeNopData routine
that actually writes PowerPC nop instructions.

This fixes the last remaining difference in object file output
(text section) between the integrated assembler and GNU as
that I've seen anywhere.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185662 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 18:28:46 +00:00
Rafael Espindola
449f64c69c Add 'not' in front of a command that is expected to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185659 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 17:21:01 +00:00
Joey Gouly
4ea250524f Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.
This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185642 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 14:57:20 +00:00
Ulrich Weigand
3c99602ca8 [PowerPC] Add all trap mnemonics
This adds support for all basic and extended variants
of the trap instructions to the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185638 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 14:40:12 +00:00
Ulrich Weigand
5606fcae50 [PowerPC] Add asm parser support for CR expressions
This adds support for specifying condition registers and
condition register fields via expressions using the symbols
defined by the PowerISA, like "4*cr2+eq".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185633 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 14:24:00 +00:00
Benjamin Kramer
32d15d90c4 SimplifyCFG: Teach switch generation some patterns that instcombine forms.
This allows us to create switches even if instcombine has munged two of the
incombing compares into one and some bit twiddling. This was motivated by enum
compares that are common in clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185632 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 14:22:02 +00:00
Joey Gouly
929d9ef111 Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185620 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 10:04:08 +00:00
Quentin Colombet
8e2e5ff024 [ARM] Improve the instruction selection of vector loads.
In the ARM back-end, build_vector nodes are lowered to a target specific
build_vector that uses floating point type. 
This works well, unless the inserted bitcasts survive until instruction
selection. In that case, they incur moves between integer unit and floating
point unit that may result in inefficient code.

In other words, this conversion may introduce artificial dependencies when the
code leading to the build vector cannot be completed with a floating point type.

In particular, this happens when loads are not aligned.

Before this patch, in that case, the compiler generates general purpose loads
and creates the floating point vector from them, instead of directly using the
vector unit.

The patch uses a vector friendly sequence of code when the inserted bitcasts to
floating point survived DAGCombine.

This is done by a target specific DAGCombine that changes the target specific
build_vector into a sequence of insert_vector_elt that get rid of the bitcasts.

<rdar://problem/14170854>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185587 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 21:42:57 +00:00
Tilmann Scheller
79c163d6dd ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb2 add immediate T3 encodings.
Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding.

The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process.

This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly.

Fixes <rdar://problem/14224440>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185575 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 20:38:01 +00:00
Ulrich Weigand
51f558c9ae [PowerPC] Support lmw/stmw in the asm parser
This adds support for the load/store multiple instructions,
currently used by the asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185564 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 18:29:47 +00:00
Ulrich Weigand
33efedc048 [PowerPC] Use mtocrf when available
Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.

Current code however always emits mtcrf.  This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible.  It does create
inefficient code with the integrated assembler, however.

To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything.  Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.

As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 17:59:07 +00:00
Rafael Espindola
73477b9f32 Prefix failing commands with not to make clear they are expected to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185554 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 16:41:29 +00:00
Rafael Espindola
621f463561 Remove another old test.
It was only passing because 'grep andpd' was not finding any andpd, but
we don't fail if part of a pipe fails.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185552 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 16:35:26 +00:00
Rafael Espindola
8b1cc1dbd8 Remove test for the old EH system. It doesn't parse anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185551 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 16:30:01 +00:00
Rafael Espindola
5b44586090 Fix test: It was missing run lines and llvm-dis has no -disable-verify option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185550 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 16:27:55 +00:00
Rafael Espindola
09a7f6016a Add support for gnu archives with a string table and no symtab.
While there, use early returns to reduce nesting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185547 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 15:57:14 +00:00
Rafael Espindola
40d40dd44e Make llvm-nm return 1 on error.
This is a small compatibility improvement with gnu nm and makes llvm-nm more
useful as a testing tool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 15:46:03 +00:00
Evgeniy Stepanov
d55ef5ce5f [msan] Unpoison stack allocations and undef values in blacklisted functions.
This changes behavior of -msan-poison-stack=0 flag from not poisoning stack
allocations to actively unpoisoning them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185538 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 14:39:14 +00:00
Ulrich Weigand
44175d9715 [PowerPC] Support mtspr/mfspr in the asm parser
This adds support for the generic forms of mtspr/mfspr
for the asm parser.  The compiler will continue to use
the specialized patters for mtlr etc. since those are
needed to correctly describe data flow.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185532 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 12:32:41 +00:00
Richard Sandiford
fa487e83a8 [SystemZ] Fold more spills
Add a mapping from register-based <INSN>R instructions to the corresponding
memory-based <INSN>.  Use it to cut down on the number of spill loads.

Some instructions extend their operands from smaller fields, so this
required a new TSFlags field to say how big the unextended operand is.

This optimisation doesn't trigger for C(G)R and CL(G)R because in practice
we always combine those instructions with a branch.  Adding a test for every
other case probably seems excessive, but it did catch a missed optimisation
for DSGF (fixed in r185435).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185529 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 10:10:02 +00:00
Mihai Popa
b81b477cd4 This corrects the implementation of Thumb ADR instruction. There are three issues:
1. it should accept only 4-byte aligned addresses
2. the maximum offset should be 1020
3. it should be encoded with the offset scaled by two bits


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185528 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 09:21:44 +00:00
Tim Northover
a10c01a6c6 ARM: relax the atomic release barrier to "dmb ishst" on Swift
Swift cores implement store barriers that are stronger than the ARM
specification but weaker than general barriers. They are, in fact, just about
enough to provide the ordering needed for atomic operations with release
semantics.

This patch makes use of that quirk.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 09:20:36 +00:00
Richard Osborne
79186beb28 [XCore] Add ISel pattern for LDWCP
Patch by Robert Lytton.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185518 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 07:48:50 +00:00
Michael Gottesman
7cbdd90982 Change the gettimeofday test to only test on a posix platform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185503 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 04:15:22 +00:00
Michael Gottesman
7cb0321ad8 Added support in FunctionAttrs for adding relevant function/argument attributes for the posix call gettimeofday.
This implies annotating it as nounwind and its arguments as nocapture. To be
conservative, we do not annotate the arguments with noalias since some platforms
do not have restrict on the declaration for gettimeofday.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185502 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 04:00:54 +00:00
Manman Ren
23f36b9225 Trying to fix the bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185489 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 00:16:11 +00:00
Manman Ren
0e6783feed Debug Info: use module flag to set up Dwarf version.
Correctly handles ref_addr depending on the Dwarf version. Emit Dwarf with
version from module flag.

TODO: turn on/off features depending on the Dwarf version.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185484 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 23:40:10 +00:00
Ulrich Weigand
25b9bbae69 [PowerPC] PR16512 - Support TLS call sequences in the asm parser
This patch now adds support for recognizing TLS call sequences in
the asm parser.  This needs a new pattern BL8_TLS, which is like
BL8_NOP_TLS except without nop.  That pattern is used for the
asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185478 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 21:31:59 +00:00