per possible ValueType of the node. e.g. Select_add is split into Select_add_i8,
Select_add_i16, etc.
For opcodes which do not produce a non-chain result, it is split on the
ValueType of its first non-chain operand. e.g. Select_store.
On X86 / Mac OS X, Select_store used to be the largest function. It had a stack
frame size of 8.5k. Now the largest one is Store_i32 with a frame size of 3.1k.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29404 91177308-0d34-0410-b5e6-96231b3b80d8
instructions not handled would have a case value of #0, throwing things off.
This marginally shrinks the X86 asmprinter, but shrinks the sparc asmwriter
by 25 lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29187 91177308-0d34-0410-b5e6-96231b3b80d8
series of identical commands, handle them all with one switch. In the case
of the x86 at&t asm printer, only 3 switches are needed for all instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29184 91177308-0d34-0410-b5e6-96231b3b80d8
based and less switch-statements-with-hundreds-of-cases based. This shrinks
the x86 asmprinters to about 1/3 their previous size.
Other improvements coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29177 91177308-0d34-0410-b5e6-96231b3b80d8
code that emit target specific nodes into emit functions that are uniquified
and shared among selection routines.
e.g. This reduces X86ISelDAGToDAG.o (release) from ~2M to ~1.5M. Stack frame
size of Select_store from ~13k down to ~8k.
This is the first step. Further work to enable more sharing will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29158 91177308-0d34-0410-b5e6-96231b3b80d8
and index into it, instead of emitting it like this:
static const char * const OpStrs[] = {
"PHINODE\n", // PHI
0, // INLINEASM
"adc ", // ADC32mi
"adc ", // ADC32mi8
...
The old way required thousands of relocations that slows down link time and
dynamic load times.
This also cuts about 10K off each of the X86 asmprinters, and should shrink
the others as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29152 91177308-0d34-0410-b5e6-96231b3b80d8
RemoveInFlightSetEntry. They are used in place of direct set operators to
reduce instruction selection function stack size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28987 91177308-0d34-0410-b5e6-96231b3b80d8
because information about one can help refine the other. This allows us to
write:
def : Pat<(i32 (extload xaddr:$src, i8)),
(LBZX xaddr:$src)>;
as:
def : Pat<(extload xaddr:$src, i8),
(LBZX xaddr:$src)>;
because tblgen knows LBZX returns i32.
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instruction, and the result type of the instruction to refine the pattern.
This allows us to write things like this:
def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
as:
def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (VR128:$src)>
and fixes a ppc64 issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28863 91177308-0d34-0410-b5e6-96231b3b80d8
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28791 91177308-0d34-0410-b5e6-96231b3b80d8
