364 Commits

Author SHA1 Message Date
Evan Cheng
28dad2a5ca Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:31:17 +00:00
Anton Korobeynikov
4878b8415f Generalize the ARM DAG combiner of mul with constants to all power-of-two cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 08:54:20 +00:00
Anton Korobeynikov
a9790d739a Some cheap DAG combine goodness for multiplication with a particular constant.
This can be extended later on to handle more "complex" constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103881 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 18:16:59 +00:00
Evan Cheng
4782b1e2ca v4i64 and v8i64 are only synthesizable when NEON is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103855 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 02:20:21 +00:00
Evan Cheng
06b666c705 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 02:18:07 +00:00
Evan Cheng
22c687b642 Added a QQQQ register file to model 4-consecutive Q registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 02:13:41 +00:00
Dan Gohman
ff7a562751 Implement a bunch more TargetSelectionDAGInfo infrastructure.
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 17:31:57 +00:00
Evan Cheng
fb3611daad Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 07:26:32 +00:00
Evan Cheng
603afbfe2a Model vld2 / vst2 with reg_sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10 17:34:18 +00:00
Jim Grosbach
4b77f6a85a Clean up the conditional for handling of sign_extend_inreg based on
whether the extract instructions are available.

rdar://7956878



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 18:34:55 +00:00
Jim Grosbach
29402132f3 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
instructions to subtarget features and update tests to reflect.
PR5717.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 23:44:43 +00:00
Jim Grosbach
b1dc393bd5 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 20:44:35 +00:00
Evan Cheng
de8aa4ed9c Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 18:28:36 +00:00
Dan Gohman
af1d8ca44a Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 00:01:06 +00:00
Dan Gohman
d858e90f03 Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 15:26:15 +00:00
Dan Gohman
1e93df6f0b Move per-function state out of TargetLowering subclasses and into
MachineFunctionInfo subclasses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 14:41:14 +00:00
Bob Wilson
9f3f061d74 Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this
may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101615 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 05:30:19 +00:00
Evan Cheng
3a1588a2e3 Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 22:20:34 +00:00
Anders Carlsson
0dbdca5a85 Fix build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101335 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 03:11:28 +00:00
Dan Gohman
46510a73e9 Add const qualifiers to CodeGen's use of LLVM IR constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 01:51:59 +00:00
Jim Grosbach
e7b52526d3 Add -arm-long-calls option to force calls to be indirect. This makes the
kernel linker happier when dealing with kexts.

Radar 7805069



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101303 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 22:28:31 +00:00
Bob Wilson
164cd8b8d3 Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand
does not have a legal type.  The legalizer does not know how to handle those
nodes.  Radar 7854640.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101282 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 20:45:23 +00:00
Bob Wilson
6a234f07fa Handle a v2f64 formal parameter that is split between registers and memory
such that the entire second half is in memory.  Radar 7855014.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101181 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 22:03:22 +00:00
Bob Wilson
d0910c4534 Expand SELECT and SELECT_CC for NEON vector types.
Radar 7770501.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100568 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-06 22:02:24 +00:00
Mon P Wang
20adc9dc46 Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100304 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-04 03:10:48 +00:00
Mon P Wang
e754d3fb85 Revert r100191 since it breaks objc in clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 18:43:02 +00:00
Mon P Wang
e33c848fa4 Reapply address space patch after fixing an issue in MemCopyOptimizer.
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100191 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 18:04:15 +00:00
Bob Wilson
100f090add Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99948 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-30 22:27:04 +00:00
Mon P Wang
808bab0169 Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99928 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-30 20:55:56 +00:00
Jim Grosbach
35075a7e81 tweak the arm if conversion heuristic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99402 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 16:15:14 +00:00
Jim Grosbach
fceabef52c try being more permissive for if-conversion on ARM V7. see what the nightly
test run permformance numbers say as to whether it helps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:03:13 +00:00
Bob Wilson
76a312b7d1 Revert this change, since it was causing ARM performance regressions.
--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99010 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 22:51:32 +00:00
Anton Korobeynikov
341ab138fb Get rid of target-specific fp <-> int nodes when still I'm here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 22:35:45 +00:00
Anton Korobeynikov
f0d500768d Get rid of target-specific nodes for fp16 <-> fp32 conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98888 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 22:35:37 +00:00
Bob Wilson
33cc5cb983 Translate "cc" clobber in ARM inline assembly to ARM::CCRRegisterClass.
Radar 7459078.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98586 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-15 23:09:18 +00:00
Bill Wendling
505ad8bed3 Now that the default for Darwin platforms is to place the LSDA into the TEXT
section, remove the target-specific code that performs this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98580 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-15 21:09:38 +00:00
Anton Korobeynikov
631379e79c Add substarget feature for FP16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98503 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:42:38 +00:00
Anton Korobeynikov
bec3dd25c7 Add codegen support for FP16 on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98502 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:42:31 +00:00
Bill Wendling
bdc38e5aa2 The ARM EH experiment worked!
Place the LSDA into the TEXT section for ARM platforms. This involves making the
encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The
references to the type infos are then non-lazy pointers. Revision 98019 changed
the encoding of non-lazy pointers to add the symbol to the non-lazy pointer
definition if it's a local symbol (otherwise, it's external and set to '0' so
that the loader can adjust it to the real value). This paved the way for this
change to work on ARM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 18:31:07 +00:00
Bill Wendling
94a1c631db This is part of an LLC-beta test used to test <rdar://problem/6804645>. Please
bear with the awful code. It won't last in its current state beyond tonight.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 02:46:12 +00:00
Bill Wendling
46ada19645 Remove dead parameter passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97536 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 01:55:18 +00:00
Bob Wilson
e742bb53a3 Check for comparisons of +/- zero when optimizing less-than-or-equal and
greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions.  This is
only allowed when UnsafeFPMath is set or when at least one of the operands
is known to be nonzero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97065 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 22:15:53 +00:00
Jim Grosbach
f9a4b7653d LowerCall() should always do getCopyFromReg() to reference the stack pointer.
Machine instruction selection is much happier when operands are in virtual
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 01:43:03 +00:00
Bob Wilson
9f6c4c141f Use NEON vmin/vmax instructions for floating-point selects.
Radar 7461718.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96572 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-18 06:05:53 +00:00
David Greene
1b58cab38c Remove an assumption of default arguments. This is in anticipation of a
change to SelectionDAG build APIs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96230 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-15 16:55:24 +00:00
Jim Grosbach
a87ded2695 tighten up eh.setjmp sequence a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95603 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-08 23:22:00 +00:00
Evan Cheng
022d9e1cef Revert 95130.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95160 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-02 23:55:14 +00:00
Evan Cheng
942619695f Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-02 21:29:10 +00:00
Anton Korobeynikov
90cfc130d6 Fix a gross typo: ARMv6+ may or may not support unaligned memory operations.
Even if they are suported by the core, they can be disabled
(this is just a configuration bit inside some register).

Allow unaligned memops on darwin and conservatively disallow them otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-30 14:08:12 +00:00
Evan Cheng
0c439eb2c8 Eliminate target hook IsEligibleForTailCallOptimization.
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94626 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-27 00:07:07 +00:00