Commit Graph

30609 Commits

Author SHA1 Message Date
Anna Zaks
ead297bb04 [asan] Do not instrument special purpose LLVM sections.
Do not instrument globals that are placed in sections containing "__llvm"
in their name.

This fixes a bug in ASan / PGO interoperability. ASan interferes with LLVM's
PGO, which places its globals into a special section, which is memcpy-ed by
the linker as a whole. When those goals are instrumented, ASan's memcpy wrapper
reports an issue.

http://reviews.llvm.org/D10541

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240723 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 23:35:48 +00:00
Anna Zaks
f291e057a4 [asan] Don't run stack malloc on functions containing inline assembly.
It makes LLVM run out of registers even on 64-bit platforms. For example, the
following test case fails on darwin.

clang -cc1 -O0 -triple x86_64-apple-macosx10.10.0 -emit-obj -fsanitize=address -mstackrealign -o ~/tmp/ex.o -x c ex.c
error: inline assembly requires more registers than available

void TestInlineAssembly(const unsigned char *S, unsigned int pS, unsigned char *D, unsigned int pD, unsigned int h) {

unsigned int sr = 4, pDiffD = pD - 5;
unsigned int pDiffS = (pS << 1) - 5;
char flagSA = ((pS & 15) == 0),
flagDA = ((pD & 15) == 0);
asm volatile (
  "mov %0,  %%"PTR_REG("si")"\n"
  "mov %2,  %%"PTR_REG("cx")"\n"
  "mov %1,  %%"PTR_REG("di")"\n"
  "mov %8,  %%"PTR_REG("ax")"\n"
  :
  : "m" (S), "m" (D), "m" (pS), "m" (pDiffS), "m" (pDiffD), "m" (sr), "m" (flagSA), "m" (flagDA), "m" (h)
  : "%"PTR_REG("si"), "%"PTR_REG("di"), "%"PTR_REG("ax"), "%"PTR_REG("cx"), "%"PTR_REG("dx"), "memory"
);
}

http://reviews.llvm.org/D10719

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240722 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 23:35:45 +00:00
Adrian Prantl
a29c6d9ea6 Debug Info: Add basic test coverage for the DWARF encoding of bitfields.
While looking at a couple of bugs in the debug info output for bitfields
I noticed that there wasn't a single regression test to test my changes
against, so here's a start.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240717 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 23:19:19 +00:00
Frederic Riss
d26d587fbe IAS: Use the root macro instanciation for location
r224810 fixed the handling of macro debug locations in AsmParser. This patch
fixes the logic to actually do what was intended: it uses the first macro of
the macro stack instead of the last one. The updated testcase shows that the
current scheme doesn't work when macro instanciations are nested and multiple
files are used.

Reviewers: compnerd

Differential Revision: http://reviews.llvm.org/D10463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240705 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 21:57:33 +00:00
Michael J. Spencer
4cbb2db3ab [Object][ELF] Add support for dumping dynamic relocations when sections are stripped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240703 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 21:47:32 +00:00
Rafael Espindola
0999c2c69c llvm-nm: Don't print mapping symbols.
This matches the behavior of gnu nm. Fixes pr23930.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240695 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 21:00:51 +00:00
Jingyue Wu
529f49db93 [InstCombine] call SimplifyICmpInst with correct context
Summary:
Fixes PR23809. Without passing the context to SimplifyICmpInst, we would
use the assume to prove that the condition feeding the assume is
trivially true (see isValidAssumeForContext in ValueTracking.cpp),
causing the removal of the assume which may be useful for later
optimizations.

Test Plan: pr23800.ll

Reviewers: hfinkel, majnemer

Reviewed By: hfinkel

Subscribers: henryhu, llvm-commits, wengxt, broune, meheff, eliben

Differential Revision: http://reviews.llvm.org/D10695

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240683 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 20:14:47 +00:00
Rafael Espindola
1de6f369b3 Diagnose undefined temporary symbols.
We already disallowed

.global .Lfoo

so this is reasonable.

This is a small cherry pick from r240130.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240681 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 20:10:45 +00:00
Paul Robinson
f2c0530fca Make this test verify .debug_pubnames is actually missing.
It was matching at EOF regardless of whether the section was present.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240679 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 19:37:13 +00:00
Peter Collingbourne
8d5e4e48bc GVN: If a branch has two identical successors, we cannot declare either dead.
This previously caused miscompilations as a result of phi nodes receiving
undef incoming values from blocks dominated by such successors.

Differential Revision: http://reviews.llvm.org/D10726

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240670 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 18:32:02 +00:00
Rafael Espindola
b12380a76d Add a test for a recent regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240656 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 16:16:08 +00:00
Rafael Espindola
bfb732def0 llvm-nm: print 'n' instead of '?'
This matches gnu nm and has the advantage that there is a upper case N.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240655 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 16:01:53 +00:00
Kit Barton
1ebbc68719 [PPC] Implement vmrgew and vmrgow instructions
This patch adds support for the vector merge even word and vector merge odd word
instructions introduced in POWER8.

Phabricator review: http://reviews.llvm.org/D10704


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240650 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 15:17:40 +00:00
Bruno Cardoso Lopes
39b2e22f00 [AsmPrinter] Fix crash in handleIndirectSymViaGOTPCRel
Check for symbols in MCValue before using them. Bail out early in case
they are null. This fixes PR23779.

Differential Revision: http://reviews.llvm.org/D10712

rdar://problem/21532830

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240649 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 15:17:23 +00:00
Artur Pilipenko
f2e7bb5d2f Take alignment into account in isSafeToLoadUnconditionally
Reviewed By: hfinkel

Differential Revision: http://reviews.llvm.org/D10475


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240636 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 12:18:43 +00:00
Toma Tabacu
e39f000353 [mips] [IAS] Fix parsing of memory offset expressions with parenthesis depth >1.
Summary:
In an expression such as "(((a+b)+c)+d)", parseParenExpression() would only parse the "a+b)+c", which would result in an error later on in the parser.
This means that we can only parse one level of inner parentheses.

In order to fix this, I added a new function called parseParenExprOfDepth(), which parses a specified number of trailing parenthesis expressions
(except for the outermost parenthesis), and changed MipsAsmParser to use it in parseMemOffset instead of parseParenExpression().

Reviewers: dsanders, rafael

Reviewed By: dsanders, rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9742

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240625 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 09:52:02 +00:00
Ahmed Bougacha
eb78c2fbdf [X86] Accept hasAVX512() as well as hasFMA() when generating FMA.
We don't always have FMA, for example when using 'clang -mavx512f'
without an explicit CPU.

Also check for an explicit +avx512f instead of CPUs in a couple
related tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240616 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 00:44:46 +00:00
Ahmed Bougacha
cd07f777e6 [X86] Cleanup fma tests a little bit. NFC.
Reformat, isolate 213->231 xform, actually --check-prefix CHECK,
and deduplicate the FMA intrinsic tests (FMA3 in AMD-land).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240615 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 00:40:25 +00:00
Swaroop Sridhar
983b80cf02 Enable StackMap Serialization for COFF
Summary

This change turns on the emission of 
__LLVM_Stackmaps section when generating COFF binaries.

Test Plan

Added a scenario to the test case: 
test\CodeGen\X86\statepoint-stackmap-format.ll.

Code Review:

http://reviews.llvm.org/D10680



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240613 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-25 00:28:42 +00:00
David Majnemer
12bb40b2ab [GVN] Intersect the IR flags when CSE'ing two instructions
We performed a simple, but incomplete, intersection when it came time to
CSE instructions.  It didn't handle, for example, the 'exact' flag.

This fixes PR23922.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240595 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 21:52:25 +00:00
David Majnemer
95a741163f [Reassociate] Don't propogate flags when creating negations
Reassociate mutated existing instructions in order to form negations
which would create additional reassociate opportunities.

This fixes PR23926.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240593 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 21:27:36 +00:00
Jingyue Wu
58f8a138a9 Add NVPTXPeephole pass to reduce unnecessary address cast
Summary:
This patch first change the register that holds local address for stack
frame to %SPL. Then the new NVPTXPeephole pass will try to scan the
following pattern

   %vreg0<def> = LEA_ADDRi64 <fi#0>, 4
   %vreg1<def> = cvta_to_local %vreg0

and transform it into

   %vreg1<def> = LEA_ADDRi64 %VRFrameLocal, 4

Patched by Xuetian Weng

Test Plan: test/CodeGen/NVPTX/local-stack-frame.ll

Reviewers: jholewinski, jingyue

Reviewed By: jingyue

Subscribers: eliben, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D10549

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240587 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 20:20:16 +00:00
Matthias Braun
7d46df3626 ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually test for it
This fixes PR23912

Differential Revision: http://reviews.llvm.org/D10620

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240582 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 20:03:27 +00:00
Alex Lorenz
c9a4f3d5d9 MIR Serialization: Serialize simple MachineRegisterInfo attributes.
This commit serializes the 3 scalar boolean attributes from the
MachineRegisterInfo class: IsSSA, TracksRegLiveness, and
TracksSubRegLiveness. These attributes are serialized as part
of the machine function YAML mapping.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10618


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240579 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 19:56:10 +00:00
Jingyue Wu
5d59315f13 [LSR] canonicalize Prod*(1<<C) to Prod<<C
Summary:
Because LSR happens at a late stage where mul of a power of 2 is
typically canonicalized to shl, this canonicalization emits code that
can be better CSE'ed.

Test Plan:
Transforms/LoopStrengthReduce/shl.ll shows how this change makes GVN more
powerful. Fixes some existing tests due to this change.

Reviewers: sanjoy, majnemer, atrick

Reviewed By: majnemer, atrick

Subscribers: majnemer, llvm-commits

Differential Revision: http://reviews.llvm.org/D10448

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240573 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 19:28:40 +00:00
Peter Collingbourne
1841925820 Object: Add XFAILed test case for r239560.
We ought to also emit unmangled references to dllimported functions,
but no existing linker needs this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240562 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 18:03:39 +00:00
Alex Lorenz
d89b55e309 MIR Serialization: Serialize the null register operands.
This commit serializes the null register machine operands.
It uses the '_' keyword to represent them, but the parser
also allows the '%noreg' named register syntax.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10580


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240558 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 17:34:58 +00:00
Michael Zolotukhin
baf8f6a261 [LoopVectorizer] Fix bailing-out condition for OptForSize case.
With option OptForSize enabled, the Loop Vectorizer is not supposed to
create tail loop. The condition checking that was invalid and was not
matching to the comment above.

Patch by Marianne Mailhot-Sarrasin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240556 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 17:26:24 +00:00
Rafael Espindola
1e6b8f552c Don't get confused with sections whose section number is reserved.
It is perfectly possible for SHNDX to contain indexes that have the same value
as reserved st_shndx values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240544 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 14:48:54 +00:00
Simon Pilgrim
1a030870fb [X86][AVX] Added full set of 256-bit vector shift tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240542 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 13:52:25 +00:00
Pawel Bylica
bf98467060 Fix instruction scheduling live register tracking
Summary:
This patch fixes PR23405 (https://llvm.org/bugs/show_bug.cgi?id=23405).

During a node unscheduling an entry in LiveRegGens can be replaced with a new value. That corrupts the live reg tracking and LiveReg* structure is not cleared as should be during unscheduling. Problematic condition that enforces Gen replacement is `I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight()`. This condition should be checked only if LiveRegGen was set in current node unscheduling.

Test Plan: Regression test included.

Reviewers: hfinkel, atrick

Reviewed By: atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9993

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240538 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 12:49:42 +00:00
Zoran Jovanovic
41f28722ef [mips][microMIPS] Implement BREAK, EHB and EI instructions
http://reviews.llvm.org/D10090


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240531 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 10:32:16 +00:00
Rafael Espindola
821b06f3a8 Change how symbol sizes are handled in lib/Object.
COFF and MachO only define symbol sizes for common symbols. Reflect that
in the class hierarchy by having a method for common symbols only in the base
and a general one in ELF.

This avoids the need of using a magic value for the size, which had a few
problems
* Most callers didn't check for it.
* The ones that did could not tell the magic value from a file actually having
  that value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240529 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 10:20:30 +00:00
Ahmed Bougacha
0810814bcc [X86] Don't generate vbroadcasti128 for v4i64 splats from memory.
We used to erroneously match:
    (v4i64 shuffle (v2i64 load), <0,0,0,0>)

Whereas vbroadcasti128 is more like:
    (v4i64 shuffle (v2i64 load), <0,1,0,1>)

This problem doesn't exist for vbroadcastf128, which kept matching
the intrinsic after r231182.  We should perhaps re-introduce the
intrinsic here as well, but that's a separate issue still being
discussed.

While there, add some proper vbroadcastf128 tests.  We don't currently
match those, like for loading vbroadcastsd/ss on AVX (the reg-reg
broadcasts where added in AVX2).

Fixes PR23886.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240488 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 00:07:16 +00:00
Ahmed Bougacha
cd5ba15e76 [X86] update_llc_test_checks vector-shuffle-*. NFC.
Some of them had gone stale.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240485 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-24 00:03:48 +00:00
Alex Lorenz
ac57f351bd MIR Serialization: Serialize immediate machine operands.
Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10573


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240481 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 23:42:28 +00:00
Alex Lorenz
926d65d4f7 MIR Parser: Use correct source locations for machine instruction diagnostics.
This commit translates the source locations for MIParser diagnostics from
the locations in the machine instruction string to the locations in the
MIR file.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10574


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240474 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 22:39:23 +00:00
Simon Pilgrim
3ebe082ff9 [X86][SSE] Added full set of 128-bit vector shift tests.
Removed some old duplicate tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240465 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 21:18:15 +00:00
Alexey Samsonov
a9a3bc268b Let llvm::ReplaceInstWithInst copy debug location from old to new instruction.
Currently some users of this function do this explicitly, and all the
rest forget to do this.

ThreadSanitizer was one of such users, and had missing debug
locations for calls into TSan runtime handling atomic operations,
eventually leading to poorly symbolized stack traces and malfunctioning
suppressions.

This is another change relevant to PR23837.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240460 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 21:00:08 +00:00
Artem Belevich
572587cad1 [NVPTX] Added missing test case for llvm.nvvm.sqrt.f NVPTX intrinsic
Differential Revision: http://reviews.llvm.org/D10663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240437 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 18:22:17 +00:00
Rafael Espindola
38e853141d Pass -m to the linker in this test.
Fixes the test on a ppc host.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240431 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 18:04:54 +00:00
Alex Lorenz
9982d6f7ee MIR Serialization: Serialize physical register machine operands.
This commit introduces functionality that's used to serialize machine operands.
Only the physical register operands are serialized by this commit.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10525


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240425 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 16:35:26 +00:00
Rafael Espindola
bd1e605b5c objdump: Don't print a (always 0) size for MachO symbols.
Only common symbol on MachO and COFF have a size.

For COFF we already had a custom format.

For MachO, there is no native objdump and we were printing it as ELF. Now
we only print the sizes for symbols that actually have them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240422 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 15:45:38 +00:00
Toma Tabacu
115be6213d [mips] [IAS] Add partial support for the ULHU pseudo-instruction.
Summary:
This only adds support for ULHU of an immediate address with/without a source register.
It does not include support for ULHU of the address of a symbol.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240410 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 14:39:42 +00:00
Petar Jovanovic
7c5bf4d38a [mips64] Emit correct addend for some PC-relative relocations
So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch
fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation.

Patch by Vladimir Radosavljevic.

Differential Revision: http://reviews.llvm.org/D10565


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240404 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 13:54:42 +00:00
Daniel Jasper
b7f5b8b4b2 Revert r240302 ("Bring r240130 back.").
This causes errors like:

  ld: error: blah.o: requires dynamic R_X86_64_PC32 reloc against '' which
  may overflow at runtime; recompile with -fPIC
  blah.cc:function f(): error: undefined reference to ''
  blah.o:g(): error: undefined reference to ''

I have not yet come up with an appropriate reproduction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240394 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 11:31:32 +00:00
Daniel Sanders
43fab48d42 [mips] llvm-readobj can parse .MIPS.abiflags. No need to check the bytes.
Summary:

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10538


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240392 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 10:11:36 +00:00
Elena Demikhovsky
d96e362b3f AVX-512: Added all forms of VPABS instruction
Added all intrinsics, tests for encoding, tests for intrinsics.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240386 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 08:19:46 +00:00
Justin Bogner
a915f41453 test: Move target dependent test in their own folder for c API test
Dissasembly tests depends on target. The problem is that it disable
all tests if all targets are not compiled. This moves things around in
order to get target specific code in a target specific folder.

Patch by Amaury Sechet. Thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240380 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 06:46:54 +00:00
Weiming Zhao
ab3926f6e4 Fix PR13851: Preserve metadata for the unswitched branch
This patch copies the metadata of the unswitched branch to the newly
crreated branch in loop unswitch pass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240378 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 05:31:09 +00:00