c1922c72ad
TableGen support for auto-generating assembly two-operand aliases.
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Assembly matchers for instructions with a two-operand form. ARM is full
of these, for example:
add {Rd}, Rn, Rm // Rd is optional and is the same as Rn if omitted.
The property TwoOperandAliasConstraint on the instruction definition controls
when, and if, an alias will be formed. No explicit InstAlias definitions
are required.
rdar://11255754
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155172 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19 23:59:23 +00:00
b423d18a00
Use a SmallVector instead of std::vector for ResOperands.
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There's almost always a small number of instruction operands, so
use a SmallVector and save on heap allocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155143 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19 17:52:34 +00:00
8caecdea56
Update some internal naming conventions to modern style.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155142 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19 17:52:32 +00:00
9b58f29ad0
Make fast isel use &XXXRegClass instead of XXXRegisterClass. Not a functional change since XXXRegisterClass is just a constant alias of &XXXRegClass, but should probably go away.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155104 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19 06:52:06 +00:00
d4824fc8aa
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 23:46:25 +00:00
b4b26f87fe
Revert "Replace some uses of std:map<std::string,...> with StringMap."
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StringMap iterators are not deterministic, and that's more important
here than speed or memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155039 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 20:24:49 +00:00
3cbcffc4e5
tblgen: remove duplicated newlines.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155038 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 19:22:47 +00:00
325478d78d
Replace some uses of std:map<std::string,...> with StringMap.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155037 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 19:13:59 +00:00
a5b0685142
Use SmallVector for the requirements on an InstAlias.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155034 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 19:02:43 +00:00
016c679c50
Tidy up. Formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155032 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 18:56:33 +00:00
bfb4327baa
Move a few more warnings to use PrintWarning().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 18:39:31 +00:00
37c53ff6a7
Tidy up. No need for a Twine here, as it's just constants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155026 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 18:39:27 +00:00
723fc11f91
Formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 18:39:23 +00:00
5bd9e0dd02
Tidy up. Add a '.' at the end of the sentence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155024 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 18:39:19 +00:00
7be43977b4
Clean up warning text. Remove extraneous prefix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155015 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 18:09:50 +00:00
9b29ea4eb3
TableGen use PrintWarning rather than fprintf(stderr,...) for warnings.
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That way we get source line number information from the diagnostics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 17:46:41 +00:00
e546c4c9c3
Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 13:02:55 +00:00
67cd20d039
Sanity check error handling for TokenAlias.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154951 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17 21:23:52 +00:00
65da6fc8af
Tidy up. 80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154881 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17 00:01:04 +00:00
b57b170317
Fix target specific intrinsic handling to adjust intrinsic number before doing attribute table lookup. Also fix attribute table lookup to handle 'invalid' intrinsic correctly. Fixes PR12542
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-13 06:14:57 +00:00
2ce182c90c
Remove incorrect comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154533 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 21:09:54 +00:00
11fc6467e6
Tidy up. Remove hard tab characters.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154532 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 21:02:33 +00:00
bf1aab1507
Tidy up. Whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154531 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 21:02:30 +00:00
ec14cd7ddc
TableGen's regpressure: emit per-registerclass weight limits.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154518 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 18:16:28 +00:00
5c1761d486
TableGen'd regpressure: register unit set pruning.
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The pruning is more complete if it is not done incrementally. The code
is also a tad less convluted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154510 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 17:35:26 +00:00
680363b5fd
Tablegen'd regpressure: emit the weighted pressure limit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154477 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 04:31:33 +00:00
aa744e2c44
Table-generated register pressure fixes.
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Handle mixing allocatable and unallocatable register gracefully.
Simplify the pruning of register unit sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154474 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 03:19:15 +00:00
4b745588c9
TableGen/reginfo potential bug: typo from previous checkin.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154452 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10 23:53:32 +00:00
0fb0678106
Fix for register pressure tables.
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Recent refactoring introduced a bug. Fix: added buildRegUnitSets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154382 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10 03:36:49 +00:00
c72e08b4a9
Use std::includes instead of my own implementation.
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Jakob's review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154377 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10 03:12:29 +00:00
176194d4ee
Added register unit sets to the target description.
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This is a new algorithm that finds sets of register units that can be
used to model registers pressure. This handles arbitrary, overlapping
register classes. Each register class is associated with a (small)
list of pressure sets. These are the dimensions of pressure affected
by the register class's liveness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154374 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10 02:25:24 +00:00
d35ac3c8bc
Added register unit weights to the target description.
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This is a new algorithm that associates registers with weighted
register units to accuretely model their effect on register
pressure. This handles registers with multiple overlapping
subregisters. It is possible, but almost inconceivable that the
algorithm fails to find an exact solution for a target description. If
an exact solution cannot be found, an inexact, but reasonable solution
will be chosen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154373 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10 02:25:21 +00:00
aec111a06b
Fix header comment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154372 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10 02:25:18 +00:00
58609b7413
Convert assert(false) followed by a return to llvm_unreachable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 04:55:46 +00:00
9b1b25f063
Tidy up spacing in some tablegen outputs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 06:52:47 +00:00
769bbfd951
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 05:20:24 +00:00
5aeda3f076
Cleanup set_union usage. The same thing but a bit cleaner now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 01:35:52 +00:00
f1275959b2
Use std::set_union instead of nasty custom code.
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I just noticed Jakob's examples of the proper application of
std::set... routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153918 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 00:47:23 +00:00
545b962f15
Second part for the 153874 one
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153875 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 15:46:46 +00:00
94338594ef
Emit the asm writer's mnemonic table with SequenceToOffsetTable.
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This way we can get AVX v-prefixed instructions tail merged with the normal insns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153869 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 09:13:46 +00:00
fab3f7ee6f
Reorder fields in MatchEntry and OperandMatchEntry to reduce padding. A bit tricky due to the target specific sizes for some of the fields so the ordering is only optimal for the targets in the tree.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153865 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 07:48:39 +00:00
7c0b3c1fb6
Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 07:01:04 +00:00
a4bd58b0f0
Use SequenceToOffsetTable to generate instruction name table for AsmWriter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153857 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 00:47:39 +00:00
413b2e7539
Use SequenceToOffsetTable to create instruction name table. Saves space particularly on X86 where AVX instructions just add a 'v' to the front of other instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153841 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-01 18:14:14 +00:00
243018ffcf
Emit the LLVM<->DWARF register mapping as a sorted table and use binary search to do the lookup.
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This also avoids emitting the information twice, which led to code bloat. On i386-linux-Release+Asserts
with all targets built this change shaves a whopping 1.3 MB off clang. The number is probably exaggerated
by recent inliner changes but the methods were already enormous with the old inline cost computation.
The DWARF reg -> LLVM reg mapping doesn't seem to have holes in it, so it could be a simple lookup table.
I didn't implement that optimization yet to avoid potentially changing functionality.
There is still some duplication both in tablegen and the generated code that should be cleaned up eventually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-01 14:23:58 +00:00
9f2a9d741f
comment typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153796 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 02:39:17 +00:00
dd9a50196c
Introduce Register Units: Give each leaf register a number.
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First small step toward modeling multi-register multi-pressure. In the
future, register units can also be used to model liveness and
aliasing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153794 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 01:35:59 +00:00
cef670a3a3
Rip out emission of the regIsInRegClass function for the asm printer.
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It's slow, bloated and completely redundant with MCRegisterClass::contains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 23:13:40 +00:00
c19f72bd83
Use SequenceToOffsetTable in emitRegisterNameString.
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This allows suffix sharing in register names. (AX is a suffix of EAX).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 21:12:52 +00:00
0d4e2ea00e
Reapply 153764 and 153761 with a fix.
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Use an explicit comparator instead of the default.
The sets are sorted, but not using the default comparator. Hopefully,
this will unbreak the Linux builders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153772 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 20:24:14 +00:00
Jim Grosbach
Craig Topper
Benjamin Kramer
Silviu Baranga
Andrew Trick
Jakob Stoklund Olesen