Commit Graph

107677 Commits

Author SHA1 Message Date
Kostya Serebryany
891198b358 [asan] Assign a low branch weight to ASan's slow path, patch by Jonas Wagner. This speeds up asan (at least on SPEC) by 1%-5% or more. Also fix lint in dfsan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216972 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 21:46:51 +00:00
Matt Arsenault
2aab51a118 R600/SI: Relax some ordering in tests.
This will help with enabling misched

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216971 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 21:45:50 +00:00
Hal Finkel
bf301d5670 Add a CFL Alias Analysis implementation
This provides an implementation of CFL alias analysis (including some
supporting data structures). Currently, we don't have any extremely fancy
features, sans some interprocedural analysis (i.e. no field sensitivity, etc.),
and we do best sitting behind BasicAA + TBAA. In such a configuration, we take
~0.6-0.8% of total compile time, and give ~7-8% NoAlias responses to queries
TBAA and BasicAA couldn't answer when bootstrapping LLVM. In testing this on
other projects, we've seen up to 10.5% of queries dropped by BasicAA+TBAA
answered with NoAlias by this algorithm.

Patch by George Burgess IV (with minor modifications by me -- mostly adapting
some BasicAA tests), thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216970 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 21:43:13 +00:00
Juergen Ributzka
a2e22cd4cd [FastISel][AArch64] Move over to target-dependent instruction selection only.
This change moves FastISel for AArch64 to target-dependent instruction selection
only. This change replicates the existing target-independent behavior, therefore
there are no changes to the unit tests or new tests.

Future changes will take advantage of this change and update functionality
and unit tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216955 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 21:32:54 +00:00
Juergen Ributzka
37753c5f9d [FastISel] Provide the option to skip target-independent instruction selection. NFC.
This allows the target to disable target-independent instruction selection and
jump directly into the target-dependent instruction selection code.

This can be beneficial for targets, such as AArch64, which could emit much
better code, but never got a chance to do so, because the target-independent
instruction selector was able to find an instruction sequence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216947 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 21:07:44 +00:00
Yi Jiang
cb2522448c Generate extract for in-tree uses if the use is scalar operand in vectorized instruction. radar://18144665
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216946 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 21:00:39 +00:00
Matt Arsenault
9c21df64a4 R600/SI: Fix hardcoded register numbers in test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216944 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 20:43:07 +00:00
Sanjay Patel
96b466c066 Refactor LowerFABS and LowerFNEG into one function (x86) (NFC)
We duplicate ~30 lines of code to lower FABS and FNEG for x86, so this patch combines them into one function. 
No functional change intended, so no additional test cases. Test-suite behavior is unchanged.

Differential Revision: http://reviews.llvm.org/D5064



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216942 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 20:24:47 +00:00
Matt Arsenault
ef02f8eb0b cmake: Don't reject unknown cpp files that start with .
Some editors create hidden file backups in the same
directory as the file, and it's annoying when cmake
errors on them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216941 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 20:20:43 +00:00
Robin Morisset
cc99164448 Fix MemoryDependenceAnalysis in cases where QueryInstr is a CmpXchg or a AtomicRMW
Summary:
MemoryDependenceAnalysis is currently cautious when the QueryInstr is an atomic
load or store, but I forgot to check for atomic cmpxchg/atomicrmw. This patch
is a way of fixing that, and making it less brittle (i.e. no risk that I forget
another possible kind of atomic, even if the IR ends up changing in the future),
by adding a fallback checking mayReadOrWriteFromMemory.

Thanks to Philip Reames for finding this bug and suggesting this solution in
http://reviews.llvm.org/D4845

Sadly, I don't see how to add a test for this, since the passes depending on
MemoryDependenceAnalysis won't trigger for an atomic rmw anyway. Does anyone
see a way for testing it?

Test Plan: none possible at first sight

Reviewers: jfb, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5019

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216940 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 20:17:52 +00:00
Sanjay Patel
4211bbc568 Fix a logic bug when copying fast-math flags.
"Setting" does not equal "copying". This bug has sat dormant for 2 reasons:
1. The unit test was not adequate.
2. Every current user of the "copyFastMathFlags" API is operating on a new instruction.
   (ie, all existing fast-math flags are off). If you copy flags to an existing
   instruction that has some flags on already, you will not necessarily turn them off
   as expected.

I uncovered this bug while trying to implement a fix for PR20802.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216939 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 20:03:00 +00:00
Rafael Espindola
6cae39f284 Add a note about AuroraUX to the release notes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216938 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 19:49:39 +00:00
Matt Arsenault
f9139d78f5 Add note to documentation about machine node chains.
I've been assuming chain operands were always the first operand,
since the documentation says this. I was confused about why they
were missing after instruction selection. Apparently the convention
changes to using the last operand for MachineSDNodes and I've never
noticed before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216934 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 19:18:52 +00:00
Matt Arsenault
f471c483e6 R600/SI: Add failing testcase.
This is broken when 64-bit add is only partially
moved to the VALU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216933 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 19:12:31 +00:00
Matt Arsenault
f7a3c7e705 Fix interference caused by fmul 2, x -> fadd x, x
If an fmul was introduced by lowering, it wouldn't be folded
into a multiply by a constant since the earlier combine would
have replaced the fmul with the fadd.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216932 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 19:02:53 +00:00
Nick Kledzik
9bf0327ea7 Code review tweaks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216931 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 18:50:24 +00:00
Matt Arsenault
0565503d5d Fix crash when looking up the addrspace of GEPs with vector types
Patch by Björn Steinbrink

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216930 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 18:47:54 +00:00
Reid Kleckner
f93099eb1c CodeGen: Handle va_start in the entry block
Also fix a small copy-paste bug in X86ISelLowering where Chain should
have been used in place of DAG.getEntryToken().

Fixes PR20828.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216929 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 18:42:44 +00:00
Matt Arsenault
1c7650f67c Fix comment and unnecessary check for FP build_vectors.
This was copy-paste from the integer version, but
FP build_vectors don't truncate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216928 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 18:33:51 +00:00
David Blaikie
fc5b232004 unique_ptrify LTOCodeGenerator::NativeObjectFile
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216927 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 18:21:06 +00:00
David Blaikie
7b96c4919a unique_ptrify the result of SpecialCaseList::create
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216925 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 18:13:54 +00:00
Hans Wennborg
fb9a3fb12d MCSchedule.h: fix VS2012 build after r216919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216924 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 18:00:00 +00:00
David Blaikie
98f518c81a unique_ptrify FileOutputBuffer::FileOutputBuffer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216921 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 17:49:23 +00:00
Alexey Samsonov
60a82bcf13 Fix left shifts of negative values in MipsDisassembler.
This bug was reported by UBSan.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216920 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 17:49:16 +00:00
Pete Cooper
6de6c6aae4 Change MCSchedModel to be a struct of statically initialized data.
This removes static initializers from the backends which generate this data, and also makes this struct match the other Tablegen generated structs in behaviour

Reviewed by Andy Trick and Chandler C

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216919 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 17:43:54 +00:00
David Blaikie
ac31076b11 unique_ptrify PBQPBuilder::build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216918 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 17:42:01 +00:00
Alexey Samsonov
93accb4815 Fix signed integer overflow in PPCInstPrinter.
This bug was reported by UBSan.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216917 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 17:38:34 +00:00
David Blaikie
7bda613297 Correct unique_ptr passing in MCObjectDisassembler::setFallbackRegion
Rather than passing by lvalue reference, pass by value to ensure that
the caller provides an rvalue (and use move assignment, rather than
release+reset, to assign to the member variable)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216916 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 17:29:51 +00:00
Alexey Samsonov
251da88db8 Fix left shifts by too large exponents in MCParser
(which happened only on error recovery path).

This bug was reported by UBSan.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216915 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 17:25:29 +00:00
Andrea Di Biagio
ca514a41ea Revert: [APFloat] Fixed a bug in method 'fusedMultiplyAdd'.
This reverts revision 216913; the new test added at revision 216913
caused regression failures on a couple of buildbots.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216914 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 17:22:49 +00:00
Andrea Di Biagio
0b6ee9fd1c [APFloat] Fixed a bug in method 'fusedMultiplyAdd'.
When folding a fused multiply-add builtin call, make sure that we propagate the
correct result in the case where the addend is zero, and the two other operands
are finite non-zero.

Example:
  define double @test() {
    %1 = call double @llvm.fma.f64(double 7.0, double 8.0, double 0.0)
    ret double %1
  }

Before this patch, the instruction simplifier wrongly folded the builtin call
in function @test to constant 'double 7.0'.
With this patch, method 'fusedMultiplyAdd' correctly evaluates the multiply and
propagates the expected result (i.e. 56.0).

Added test fold-builtin-fma.ll with the reproducible from PR20832 plus extra
test cases to verify the behavior of method 'fusedMultiplyAdd' in the presence
of NaN/Inf operands.

This fixes PR20832.

Differential Revision: http://reviews.llvm.org/D5152


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216913 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 16:44:56 +00:00
JF Bastien
a778b5efaa Add missing override on ARMAsmBackend's dtor.
Test Plan: ninja check && ninja clang-test

Subscribers: aemerson

Differential Revision: http://reviews.llvm.org/D5075

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216912 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 16:26:55 +00:00
David Majnemer
9e1f653e2f LICM: Don't crash when an instruction is used by an unreachable BB
Summary:
BBs might contain non-LCSSA'd values after the LCSSA pass is run if they
are unreachable from the entry block.

Normally, the users of the instruction would be PHIs but the unreachable
BBs have normal users; rewrite their uses to be undef values.

An alternative fix could involve fixing this at LCSSA but that would
require this invariant to hold after subsequent transforms.  If a BB
created an unreachable block, they would be in violation of this.

This fixes PR19798.

Differential Revision: http://reviews.llvm.org/D5146

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216911 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 16:22:00 +00:00
Alexey Samsonov
4648487925 Fix left shifts of negative integers in AArch64 InstPrinter/Disassembler
Summary:
Left shift of negative integer is an undefined behavior, and
is reported by UBSan. It's ok for imm values to be negative, so we can
just replace left shifts with multiplications.

Test Plan: check-llvm test suite

Reviewers: t.p.northover

Reviewed By: t.p.northover

Subscribers: aemerson, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D5132

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216910 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 16:19:41 +00:00
Hal Finkel
2633f795c6 Enable splitting indexing from loads with TargetConstants
When I recommitted r208640 (in r216898) I added an exclusion for TargetConstant
offsets, as there is no guarantee that a backend can handle them on generic
ADDs (even if it generates them during address-mode matching) -- and,
specifically, applying this transformation directly with TargetConstants caused
a self-hosting failure on PPC64. Ignoring all TargetConstants, however, is less
than ideal. Instead, for non-opaque constants, we can convert them into regular
constants for use with the generated ADD (or SUB).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216908 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 16:05:23 +00:00
Rafael Espindola
1e556a80ff Replace -use-init-array with -use-ctors.
We have been using .init-array for most systems for quiet some time,
but tools like llc are still defaulting to .ctors because the old
option was never changed.

This patch makes llc default to .init-array and changes the option to
be -use-ctors.

Clang is not affected by this. It has its own fancier logic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216905 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 13:54:53 +00:00
Aaron Ballman
edc658d686 Silencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)). NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216902 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 12:19:02 +00:00
David Xu
4e2b661005 Merge Extend and Shift into a UBFX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216899 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 09:33:56 +00:00
Hal Finkel
3da41a28a1 Revert "Revert '[DAGCombiner] Split up an indexed load if only the base pointer value is live'"
I reverted r208640 in r209747 because r208640 broke self-hosting on PPC64. The
underlying cause of the failure is that pre-inc loads with increments
represented by ISD::TargetConstants were being transformed into ISD:::ADDs with
ISD::TargetConstant operands. PPC doesn't have a pattern for those, and so they
were selected as invalid r+r adds.

This recommits r208640, rebased and with an exclusion for ISD::TargetConstant
increments. This behavior seems correct, although in the future we might want
to ask the target to split out the indexing that uses ISD::TargetConstants.

Unfortunately, I don't yet have small test case where the relevant invalid
'add' instruction is not itself dead (and thus eliminated by
DeadMachineInstructionElim -- sometimes bugpoint is too good at removing things)

Original commit message (by Adam Nemet):

Right now the load may not get DCE'd because of the side-effect of updating
the base pointer.

This can happen if we lower a read-modify-write of an illegal larger type
(e.g. i48) such that the modification only affects one of the subparts (the
lower i32 part but not the higher i16 part).  See the testcase.

In order to spot the dead load we need to revisit it when SimplifyDemandedBits
decided that the value of the load is masked off.  This is the
CommitTargetLoweringOpt piece.

I checked compile time with ARM64 by sending SPEC bitcode files through llc.
No measurable change.

Fixes <rdar://problem/16031651>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216898 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 06:24:04 +00:00
Hal Finkel
dea837d3c5 [PowerPC] Guard against illegal selection of add for TargetConstant operands
r208640 was reverted because it caused a self-hosting failure on ppc64. The
underlying cause was the formation of ISD::ADD nodes with ISD::TargetConstant
operands. Because we have no patterns for 'add' taking 'timm' nodes, these are
selected as r+r add instructions (which is a miscompile). Guard against this
kind of behavior in the future by making the backend crash should this occur
(instead of silently generating invalid output).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216897 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 06:23:54 +00:00
Saleem Abdulrasool
901a3419d1 CodeGen: indicate Windows unwind data format
The structures for Windows unwinding are shared across multiple platforms.
Indicate the encoding to be used for the particular target.  Use this to switch
the unwind emitter instantiated by the AsmPrinter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216895 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-01 23:48:39 +00:00
Saleem Abdulrasool
05c3ddfa4e CodeGen: split out the Win64Exception emitter
Move the Windows unwind information emitter into a separate header.  This is not
related to DWARF based emission.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216894 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-01 23:48:34 +00:00
Saleem Abdulrasool
0c1740ce1a MC: remove unnecessary enumeration prefix
This is an enum class, and will be appropriately prefixed, making the encoding
type prefix redundant.  No change to any uses as the use of this was not yet
introduced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216893 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-01 23:48:29 +00:00
David Majnemer
e64e7c4634 SROA: Don't insert instructions before a PHI
SROA may decide that it needs to insert a bitcast and would set it's
insertion point before a PHI.  This will create an invalid module
right quick.

Instead, choose the first insertion point in the basic block that holds
our PHI.

This fixes PR20822.

Differential Revision: http://reviews.llvm.org/D5141

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216891 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-01 21:20:14 +00:00
David Majnemer
a0b2af46a5 Revert "Revert two GEP-related InstCombine commits"
This reverts commit r216698 which reverted r216523 and r216598.

We would attempt to perform the transformation even if the match()
failed because, as a side effect, it would set V.  This would trick us
into believing that we correctly found a place to correctly apply the
transform.

An additional test case was added to getelementptr.ll so that we might
not regress in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216890 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-01 21:10:02 +00:00
Sanjay Patel
3c7bd3fbef Use an integer constant for FABS / FNEG (x86).
This change will ease refactoring LowerFABS() and LowerFNEG() 
since they have a lot of overlap.

Remove the creation of a floating point constant from an integer
because it's going to be used for a bitwise integer op anyway.

No change to codegen expected, but the verbose comment string
for asm output may change from float values to hex (integer),
depending on whether the constant already exists or not.

Differential Revision: http://reviews.llvm.org/D5052



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216889 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-01 19:01:47 +00:00
Sanjay Patel
73f8eff19e Add a convenience method to copy wrapping, exact, and fast-math flags (NFC).
The loop vectorizer preserves wrapping, exact, and fast-math properties of scalar instructions.
This patch adds a convenience method to make that operation easier because we need to do this
in the loop vectorizer, SLP vectorizer, and possibly other places.

Although this is a 'no functional change' patch, I've added a testcase to verify that the exact
flag is preserved by the loop vectorizer. The wrapping and fast-math flags are already checked
in existing testcases.

Differential Revision: http://reviews.llvm.org/D5138



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216886 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-01 18:44:57 +00:00
Jingyue Wu
88350bf61d Fix a typo in comments in r216862, NFC
PR20766 -> PR20776. Thanks Roman Divacky for the catch!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216883 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-01 14:55:04 +00:00
Tilmann Scheller
4016a9ea4a [ARM] Add Thumb-2 code size optimization regression test for EOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216881 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-01 12:59:34 +00:00
Tilmann Scheller
9e6f09d7ce ARM] Add Thumb-2 code size optimization regression test for BIC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216880 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-01 12:53:29 +00:00