Commit Graph

453 Commits

Author SHA1 Message Date
Manman Ren
cbafae6d33 Debug Info: clean up usage of Verify.
No functionality change.
It should suffice to check the type of a debug info metadata, instead of
calling Verify. For cases where we know the type of a DI metadata, use
assert.

Also update testing cases to make them conform to the format of DI classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-28 05:43:10 +00:00
Justin Holewinski
c2b7f5fa51 Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.
The intrinsic calls are dropped, but the annotated value is propagated.

Fixes PR 15253

Original patch by Zeng Bin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182387 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 14:37:16 +00:00
Manman Ren
2dc50d3067 TBAA: remove !tbaa from testing cases if not used.
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180796 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 17:52:57 +00:00
Jyotsna Verma
da32db45fd XFAIL some of the generic CodeGen tests for Hexagon.
test/CodeGen/Generic/2008-02-20-MatchingMem.ll: Test contains inline assembly not supported by Hexagon.

Following tests are XFAILed due to multiple return values which Hexagon doesn't support.

test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll
test/CodeGen/Generic/select-cc.ll
test/CodeGen/Generic/vector.ll



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177912 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 21:04:16 +00:00
Hao Liu
d73795f07e Add a test case for PR15318 fixed in r177472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177489 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20 06:18:06 +00:00
Eric Christopher
fffe363493 For inline asm:
- recognize string "{memory}" in the MI generation
- mark as mayload/maystore when there's a memory clobber constraint.

PR14859.

Patch by Krzysztof Parzyszek

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11 18:12:39 +00:00
Nadav Rotem
bf5a2c6a39 After reducing the size of an operation in the DAG we zero-extend the reduced
bitwidth op back to the original size. If we reduce ANDs then this can cause
an endless loop. This patch changes the ZEXT to ANY_EXTEND if the demanded bits
are equal or smaller than the size of the reduced operation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170505 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 07:39:08 +00:00
Paul Redmond
0a0990af1c move X86-specific test
This test case uses -mcpu=corei7 so it belongs in CodeGen/X86

Reviewed by: Nadav


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169801 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 00:36:43 +00:00
Duncan Sands
b2df01ab2a Codegen support for arbitrary vector getelementptrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167830 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 13:01:58 +00:00
Manman Ren
1a710fdde1 BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle
the case of multiple edges from one block to another.

A simple example is a switch statement with multiple values to the same
destination. The definition of an edge is modified from a pair of blocks to
a pair of PredBlock and an index into the successors.

Also set the weight correctly when building SelectionDAG from LLVM IR,
especially when converting a Switch.
IntegersSubsetMapping is updated to calculate the weight for each cluster.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162572 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 18:14:27 +00:00
Benjamin Kramer
4e81d40545 Fix broken check lines.
I really need to find a way to automate this, but I can't come up with a regex
that has no false positives while handling tricky cases like custom check
prefixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17 12:28:26 +00:00
Eli Friedman
6b951b25c3 The normal edge of an invoke is not allowed to branch to a block with a
landingpad.  Enforce it in the verifier, and fix the regression tests to match.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161697 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 20:55:20 +00:00
Nadav Rotem
46646572f7 Fix a bug in the scalarization of BUILD_VECTOR. BUILD_VECTOR elements may be wider than the output element type. Make sure to trunc them if needed.
Together with Michael Kuperstein <michael.m.kuperstein@intel.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160235 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15 20:39:08 +00:00
Bob Wilson
30a507a1f5 Extend TargetPassConfig to allow running only a subset of the normal passes.
This is still a work in progress but I believe it is currently good enough
to fix PR13122 "Need unit test driver for codegen IR passes".  For example,
you can run llc with -stop-after=loop-reduce to have it dump out the IR after
running LSR.  Serializing machine-level IR is not yet supported but we have
some patches in progress for that.

The plan is to serialize the IR to a YAML file, containing separate sections
for the LLVM IR, machine-level IR, and whatever other info is needed.  Chad
suggested that we stash the stop-after pass in the YAML file and use that
instead of the start-after option to figure out where to restart the
compilation.  I think that's a great idea, but since it's not implemented yet
I put the -start-after option into this patch for testing purposes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159570 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 19:48:45 +00:00
Chandler Carruth
49589f0d0e Convert the uses of '|&' to use '2>&1 |' instead, which works on old
versions of Bash. In addition, I can back out the change to the lit
built-in shell test runner to support this.

This should fix the majority of fallout on Darwin, but I suspect there
will be a few straggling issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159544 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 18:37:59 +00:00
Nuno Lopes
85b408991a add a new @llvm.donothing intrinsic that, well, does nothing, and teach CodeGen to ignore calls to it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159383 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28 22:30:12 +00:00
Rafael Espindola
275c85f1a7 Fix llc's -print-before=pass and -print-after=pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159227 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26 21:33:36 +00:00
Jack Carter
0518fca843 There are a number of generic inline asm operand modifiers that
up to r158925 were handled as processor specific. Making them 
generic and putting tests for these modifiers in the CodeGen/Generic
directory caused a number of targets to fail. 

This commit addresses that problem by having the targets call 
the generic routine for generic modifiers that they don't currently
have explicit code for.

For now only generic print operands 'c' and 'n' are supported.vi


Affected files:

    test/CodeGen/Generic/asm-large-immediate.ll
    lib/Target/PowerPC/PPCAsmPrinter.cpp
    lib/Target/NVPTX/NVPTXAsmPrinter.cpp
    lib/Target/ARM/ARMAsmPrinter.cpp
    lib/Target/XCore/XCoreAsmPrinter.cpp
    lib/Target/X86/X86AsmPrinter.cpp
    lib/Target/Hexagon/HexagonAsmPrinter.cpp
    lib/Target/CellSPU/SPUAsmPrinter.cpp
    lib/Target/Sparc/SparcAsmPrinter.cpp
    lib/Target/MBlaze/MBlazeAsmPrinter.cpp
    lib/Target/Mips/MipsAsmPrinter.cpp
    
MSP430 isn't represented because it did not even run with
the long existing 'c' modifier and it was not apparent what
needs to be done to get it inline asm ready.

Contributer: Jack Carter



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26 13:49:27 +00:00
Jakob Stoklund Olesen
a4e6397fd9 Enforce stricter liveness rules for PHIs.
Verify that all paths from the entry block to a virtual register read
pass through a def. Enable this check even when MRI->isSSA() is false.

Verify that the live range of a virtual register is live out of all
predecessor blocks, even for PHI-values.

This requires that PHIElimination sometimes inserts IMPLICIT_DEF
instruction in predecessor blocks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-25 18:18:27 +00:00
NAKAMURA Takumi
84f64f317f test/CodeGen/Generic/asm-large-immediate.ll: Mark it as XFAIL: powerpc, possibly due to r158939.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158994 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22 13:41:00 +00:00
Jack Carter
4db98becf7 The inline asm operand modifier 'n' is suppose
to be generic across architectures. It has the
following description in the gnu sources:

    Negate the immediate constant

Several Architectures such as x86 have local implementations
of operand modifier 'n' which go beyond the above description
slightly. This won't affect them.

Affected files:

    lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
        Added 'n' to the switch cases.

    test/CodeGen/Generic/asm-large-immediate.ll
        Generic compiled test (x86 for me)

    test/CodeGen/Mips/asm-large-immediate.ll
        Mips compiled version of the generic one

Contributer: Jack Carter



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158939 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21 21:37:54 +00:00
NAKAMURA Takumi
e42e9ce20f Revert r158209, "test/CodeGen/Generic/APIntLoadStore.ll: Mark as XFAIL:ppc since r157911."
It passes according to ppc changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158917 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21 13:43:06 +00:00
Jakob Stoklund Olesen
7ed1ad54f2 Fix test case to work on ARM.
Patch by James Benton!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158316 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11 16:01:14 +00:00
Jakob Stoklund Olesen
6660ed5f2f Don't run RAFast in the optimizing regalloc pipeline.
The fast register allocator is not supposed to work in the optimizing
pipeline. It doesn't make sense to compute live intervals, run full copy
coalescing, and then run RAFast.

Fast register allocation in the optimizing pipeline is better done by
RABasic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158242 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08 23:15:12 +00:00
Chad Rosier
28dd960cd1 Fix a crash in APInt::lshr when shiftAmt > BitWidth.
Patch by James Benton <jbenton@vmware.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158213 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08 18:04:52 +00:00
NAKAMURA Takumi
7c18922f85 test/CodeGen/Generic/APIntLoadStore.ll: Mark as XFAIL:ppc since r157911.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158209 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08 16:28:06 +00:00
Bob Wilson
6e1b812850 Add an insertPass API to TargetPassConfig. <rdar://problem/11498613>
Besides adding the new insertPass function, this patch uses it to
enhance the existing -print-machineinstrs so that the MachineInstrs
after a specific pass can be printed.

Patch by Bin Zeng!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 00:17:12 +00:00
Nuno Lopes
23e75da7e0 revert my previous patches that introduced an additional parameter to the objectsize intrinsic.
After a lot of discussion, we realized it's not the best option for run-time bounds checking

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-22 15:25:31 +00:00
Nuno Lopes
30759542aa change the objectsize intrinsic signature: add a 3rd parameter to denote the maximum runtime performance penalty that the user is willing to accept.
This commit only adds the parameter. Code taking advantage of it will follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156473 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09 15:52:43 +00:00
Bill Wendling
57ca13ecc4 Move to X86 directory because this fails on non-X86 platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154825 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 16:38:48 +00:00
Rafael Espindola
fdb230a154 Don't try to zExt just to check if an integer constant is zero, it might
not fit in a i64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154364 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10 00:16:22 +00:00
Pete Cooper
2ce63c7352 Add VSELECT to LegalizeVectorTypes::ScalariseVectorResult. Previously it would crash if it encountered a 1 element VSELECT. Solution is slightly more complicated than just creating a SELET as we have to mask or sign extend the vector condition if it had different boolean contents from the scalar condition. Fixes <rdar://problem/11178095>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153976 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 22:57:55 +00:00
Bill Wendling
4108bd3780 Add testcase for r153705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153706 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 00:05:02 +00:00
Andrew Trick
07269265b0 misched: tag a few XFAILs that I plan to fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153222 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 22:31:31 +00:00
Andrew Trick
10fa51b950 I meant to disable this test, not XFAIL it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153165 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 05:18:53 +00:00
Andrew Trick
c6a19dd7fb misched: beginning to add unit tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153163 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 04:12:19 +00:00
Eli Bendersky
0f0c411079 Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 06:28:33 +00:00
NAKAMURA Takumi
7a73925c50 Move test/CodeGen/Generic/2012-02-01-CoalescerBug.ll to CodeGen/ARM, for now. It requires TARGETS=arm.
I cannot reproduce a fixed issue with other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 11:44:58 +00:00
Lang Hames
02e08d5b4d PR11868. The previous loop in LiveIntervals::join would sometimes fall over if
more than two adjacent ranges needed to be merged. The new version should be
able to handle an arbitrary sequence of adjancent ranges.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 05:37:34 +00:00
Bill Wendling
1fe1adeeba Remove all references to the old EH.
There was always the current EH. -- Ministry of Truth


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149335 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31 02:09:07 +00:00
Chandler Carruth
ddbc274169 Manually upgrade the test suite to specify the flag to cttz and ctlz.
I followed three heuristics for deciding whether to set 'true' or
'false':

- Everything target independent got 'true' as that is the expected
  common output of the GCC builtins.
- If the target arch only has one way of implementing this operation,
  set the flag in the way that exercises the most of codegen. For most
  architectures this is also the likely path from a GCC builtin, with
  'true' being set. It will (eventually) require lowering away that
  difference, and then lowering to the architecture's operation.
- Otherwise, set the flag differently dependending on which target
  operation should be tested.

Let me know if anyone has any issue with this pattern or would like
specific tests of another form. This should allow the x86 codegen to
just iteratively improve as I teach the backend how to differentiate
between the two forms, and everything else should remain exactly the
same.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 11:59:10 +00:00
Nadav Rotem
ea6578b72a Remove the the test which checks the saving of a vector of booleans into memory.
The decision was to pack the bits. Currently no codegen supports this.
Currently, all of the bits in the vector are saved into the same address
in memory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142149 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 19:06:06 +00:00
David Meyer
8f418b11d2 PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 06:13:20 +00:00
Bill Wendling
4d1d86bac9 This test is completely invalid with the modern EH model. Delete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140213 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 23:52:09 +00:00
Nadav Rotem
4b36e07487 This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139288 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 08:43:23 +00:00
Nadav Rotem
ffe3e7da84 Add X86-SSE4 codegen support for vector-select.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 08:11:19 +00:00
Dan Gohman
b116142d3b Revert r129875, XFAILing this test for arm, since the fix was reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:14:24 +00:00
Bill Wendling
47e208bbea Try to eliminate the use of the 'unwind' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 22:41:11 +00:00
Benjamin Kramer
bcf47a5bce XFAIL this test on arm until the backend is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138955 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 18:40:03 +00:00
Bill Wendling
fd245d97f1 Revert r138894. This was failing on cmake-clang-i686-msvc10.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 21:20:25 +00:00