Commit Graph

805 Commits

Author SHA1 Message Date
Duncan Sands
28b77e968d Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 19:07:46 +00:00
Benjamin Kramer
deaa64546e Roll back the rest of r126557. It's a hack that will break in some obscure cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138130 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 22:39:31 +00:00
Nadav Rotem
c796ae1d68 Revert r137310 because it does not optimize any code on ToT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137466 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 17:15:04 +00:00
Nadav Rotem
f80a894bf0 [AVX] When joining two XMM registers into a YMM register, make sure that the
lower XMM register gets in first. This will allow the SUBREG pattern to
elliminate the first vector insertion. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137310 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 16:49:36 +00:00
Eli Friedman
ed4b4272ba Make sure this DAGCombine actually returns an UNDEF of the correct type; PR10476.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135993 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 22:25:42 +00:00
Chris Lattner
db125cfaf5 land David Blaikie's patch to de-constify Type, with a few tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 04:54:35 +00:00
Eric Christopher
7332e6ee25 Add a dag combine pattern for folding C2-(A+C1) -> (C2-C1)-A
Fixes rdar://9761830

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 01:12:15 +00:00
Lang Hames
944520f38c Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. The
hasPredecessorHelper function allows predecessors to be cached to speed up
repeated invocations. This fixes PR10186.

X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X)

Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with
empty Visited and Worklist sets (i.e. no caching over invocations).

Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited
and Worklist to speed up repeated calls. The Visited set is searched for X
before going to the worklist to further search the DAG if necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 04:31:51 +00:00
Benjamin Kramer
bdd1ef2dbe Revert a part of r126557 which could create unschedulable DAGs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134067 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 13:47:25 +00:00
Jay Foad
267010864e Replace the existing forms of ConstantArray::get() with a single form
that takes an ArrayRef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133615 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22 09:24:39 +00:00
Evan Cheng
9568e5c3c3 Teach dag combine to match halfword byteswap patterns.
1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)
   => (bswap x) >> 16
2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8))
   => (rotl (bswap x) 16)

This allows us to eliminate most of the def : Pat patterns for ARM rev16
revsh instructions. It catches many more cases for ARM and x86.

rdar://9609108


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133503 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21 06:01:08 +00:00
Nick Lewycky
c06b5bf340 Add a DAGCombine for (ext (binop (load x), cst)).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16 01:15:49 +00:00
Nadav Rotem
baff46f192 Enable the simplification of truncating-store after fixing the usage of
GetDemandBits (which must operate on the vector element type).

Fix the a usage of getZeroExtendInReg which must also be done on scalar types.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133052 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 11:19:12 +00:00
Chad Rosier
92bcd96bbc When pattern matching during instruction selection make sure shl x,1 is not
converted to add x,x if x is a undef.  add undef, undef does not guarantee
that the resulting low order bit is zero.
Fixes <rdar://problem/9453156> and <rdar://problem/9487392>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14 22:29:10 +00:00
Nadav Rotem
c7cb7ed013 Disable trunc-store simplification on vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132984 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14 07:18:26 +00:00
Eli Friedman
2a6d9eb10b Change this DAGCombine to build AND of SHR instead of SHR of AND; this matches the ordering we prefer in instcombine. Part of rdar://9562809.
The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132809 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 22:14:44 +00:00
Devang Patel
9728ea2447 Revert 121907 (it causes llc crash) and apply original patch from PR9817.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131926 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 22:04:42 +00:00
Benjamin Kramer
f55d26e788 Implement mulo x, 2 -> addo x, x in DAGCombiner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131800 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-21 18:31:55 +00:00
Dan Gohman
71dc7c9d89 Misc. code cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 22:20:36 +00:00
Nadav Rotem
42febc6e99 Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain).
If there is a store after the load node, then there is a chain, which means
that there is another user. Thus, asking hasOneUser would fail. Instead we
ask hasNUsesOfValue on the 'data' value.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131183 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-11 14:40:50 +00:00
Duncan Sands
c356f33aaf Indent properly, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-09 08:03:33 +00:00
Eli Friedman
e545d38a28 PR9055: extend the fix to PR4050 (r70179) to apply to zext and anyext.
Returning a new node makes the code try to replace the old node, which
in the included testcase is killed by CSE.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129650 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-16 23:25:34 +00:00
Owen Anderson
a34d93630e Fix another instance of the DAG combiner not using the correct type for the RHS of a shift.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 17:30:49 +00:00
Chris Lattner
b3452ea35c have dag combine zap "store undef", which can be formed during call lowering
with undef arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129185 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09 02:32:02 +00:00
Cameron Zwarich
ed3caf9086 Add a RemoveFromWorklist method to DCI. This is needed to do some complicated
transformations in target-specific DAG combines without causing DAGCombiner to
delete the same node twice. If you know of a better way to avoid this (see my
next patch for an example), please let me know.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128758 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 02:40:26 +00:00
Evan Cheng
9ef82ce4fe Avoid replacing the value of a directly stored load with the stored value if the load is indexed. rdar://9117613.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 00:48:56 +00:00
Stuart Hastings
7e33418671 Can't introduce floating-point immediate constants after legalization.
Radar 9056407.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02 19:36:30 +00:00
Nadav Rotem
fcd96199f5 Fix typos in the comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-27 07:40:43 +00:00
Benjamin Kramer
7466678003 Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic.
1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible

It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-26 22:48:07 +00:00
Owen Anderson
95771afbfd Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25 21:41:48 +00:00
Nadav Rotem
8c20ec54d9 Enable support for vector sext and trunc:
Limit the folding of any_ext and sext  into the load operation to scalars.
Limit the active-bits trunc optimization to scalars.
Document vector trunc and vector sext in LangRef.

Similar to commit 126080 (for enabling zext).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 21:01:34 +00:00
Nadav Rotem
ed9b934f65 Fix 9267; Add vector zext support.
The DAGCombiner folds the zext into complex load instructions. This patch
prevents this optimization on vectors since none of the supported targets
knows how to perform load+vector_zext in one instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-20 12:37:50 +00:00
Stuart Hastings
a901129169 Swap VT and DebugLoc operands of getExtLoad() for consistency with
other getNode() methods.  Radar 9002173.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-16 16:23:55 +00:00
Eric Christopher
7bccf6abdc Refactor zero folding slightly. Clean up todo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125651 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-16 04:50:12 +00:00
Eric Christopher
169e1552e7 The change for PR9190 wasn't quite right. We need to avoid making the
transformation if we can't legally create a build vector of the correct
type. Check that we can make the transformation first, and add a TODO to
refactor this code with similar cases.

Fixes: PR9223 and rdar://9000350


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-16 01:10:03 +00:00
Chris Lattner
e075118489 Revisit my fix for PR9028: the issue is that DAGCombine was
generating i8 shift amounts for things like i1024 types.  Add
an assert in getNode to prevent this from occuring in the future,
fix the buggy transformation, revert my previous patch, and
document this gotcha in ISDOpcodes.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125465 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-13 19:09:16 +00:00
Nadav Rotem
609d54ee1e A fix for 9165.
The DAGCombiner created illegal BUILD_VECTOR operations.
The patch added a check that either illegal operations are
allowed or that the created operation is legal.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125435 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-12 14:40:33 +00:00
Nadav Rotem
f94fdb6f57 SimplifySelectOps can only handle selects with a scalar condition. Add a check
that the condition is not a vector.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125398 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-11 19:57:47 +00:00
Nadav Rotem
5a4552ca42 Fix #9190
The bug happens when the DAGCombiner attempts to optimize one of the patterns
of the SUB opcode. It tries to create a zero of type v2i64. This type is legal
on 32bit machines, but the initializer of this vector (i64) is target dependent.
Currently, the initializer attempts to create an i64 zero constant, which fails.
Added a flag to tell the DAGCombiner to create a legal zero, if we require that
the pass would generate legal types.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125391 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-11 19:20:37 +00:00
Evan Cheng
31959b19a7 Given a pair of floating point load and store, if there are no other uses of
the load, then it may be legal to transform the load and store to integer
load and store of the same width.

This is done if the target specified the transformation as profitable. e.g.
On arm, this can transform:
vldr.32 s0, []
vstr.32 s0, []

to

ldr r12, []
str r12, []

rdar://8944252


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-02 01:06:55 +00:00
Richard Osborne
4e3740ee6d Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-31 17:41:44 +00:00
Benjamin Kramer
9b108a338d Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2) when c1 equals the amount of bits that are truncated off.
This happens all the time when a smul is promoted to a larger type.

On x86-64 we now compile "int test(int x) { return x/10; }" into
  movslq  %edi, %rax
  imulq $1717986919, %rax, %rax
  movq  %rax, %rcx
  shrq  $63, %rcx
  sarq  $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax"
  addl  %ecx, %eax

This fires 96 times in gcc.c on x86-64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-30 16:38:43 +00:00
Benjamin Kramer
2c94b4201b Add the missing sub identity "A-(A-B) -> B" to DAGCombine.
This happens e.g. for code like "X - X%10" where we lower the modulo operation
to a series of multiplies and shifts that are then subtracted from X, leading to
this missed optimization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124532 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-29 12:34:05 +00:00
Anton Korobeynikov
16c29b5f28 Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10 12:39:04 +00:00
Benjamin Kramer
f50125ecaa DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is illegal. The latter usually compiles into smaller code.
example code:
unsigned foo(unsigned x, unsigned y) {
  if (x != 0) y--;
  return y;
}

before:
  _foo:                           ## @foo
    cmpl  $1, 4(%esp)             ## encoding: [0x83,0x7c,0x24,0x04,0x01]
    sbbl  %eax, %eax              ## encoding: [0x19,0xc0]
    notl  %eax                    ## encoding: [0xf7,0xd0]
    addl  8(%esp), %eax           ## encoding: [0x03,0x44,0x24,0x08]
    ret                           ## encoding: [0xc3]

after:
  _foo:                           ## @foo
    cmpl  $1, 4(%esp)             ## encoding: [0x83,0x7c,0x24,0x04,0x01]
    movl  8(%esp), %eax           ## encoding: [0x8b,0x44,0x24,0x08]
    adcl  $-1, %eax               ## encoding: [0x83,0xd0,0xff]
    ret                           ## encoding: [0xc3]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22 23:17:45 +00:00
Chris Lattner
cbf68dfbc0 Fix a bug in ReduceLoadWidth that wasn't handling extending
loads properly.  We miscompiled the testcase into:

_test:                                  ## @test
	movl	$128, (%rdi)
	movzbl	1(%rdi), %eax
	ret

Now we get a proper:

_test:                                  ## @test
	movl	$128, (%rdi)
	movsbl	(%rdi), %eax
	movzbl	%ah, %eax
	ret

This fixes PR8757.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122392 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22 08:02:57 +00:00
Chris Lattner
7a2a7faf9c more cleanups, move a check for "roundedness" earlier to reject
unhanded cases faster and simplify code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122391 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22 08:01:44 +00:00
Chris Lattner
4c32bc24de reduce indentation and improve comments, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122389 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22 07:36:50 +00:00
Dale Johannesen
c72b18cdc8 Reapply 122353-122355 with fixes. 122354 was wrong;
the shift type was needed one place, the shift count
type another.  The transform in 123555 had the same
problem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 21:55:50 +00:00
Dale Johannesen
d0cf2585a0 Revert 122353-122355 for the moment, they broke stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21 21:22:27 +00:00