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20837 Commits

Author SHA1 Message Date
Akira Hatanaka
ef43c2de86 32-to-64-bit sext_inreg pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147004 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:40:40 +00:00
Akira Hatanaka
acb5a06f7a Add 64-bit extload patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:36:08 +00:00
Akira Hatanaka
ab05b6c227 Add patterns for matching extloads with 64-bit address. The patterns are enabled 
only when the target ABI is N64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147001 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:33:53 +00:00
Jim Grosbach
3cbe43fe69 Move comment to appropriate place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147000 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:26:38 +00:00
Akira Hatanaka
990d639f55 Add code in MipsDAGToDAGISel for selecting constant +0.0. 
MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146999 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:25:50 +00:00
Jakob Stoklund Olesen
52346e964f Heed spill slot alignment on ARM. 
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.

Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack.  Don't use aligned spill code in that case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:15:04 +00:00
Akira Hatanaka
05c585319b Revert part of r146995 that was accidentally commmitted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146996 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:09:36 +00:00
Akira Hatanaka
403992dc58 32-to-64-bit sign extension pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:06:20 +00:00
Akira Hatanaka
caace8abdf Add a pattern for matching zero-store with 64-bit address. The pattern is enabled 
only when the target ABI is N64. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146992 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 21:50:49 +00:00
Jim Grosbach
5b484312c6 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 20:46:29 +00:00
Jim Grosbach
95fad1c603 ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 19:21:26 +00:00
Evan Cheng
afff941211 ARM target code clean up. Check for iOS, not Darwin where it makes sense. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 18:26:50 +00:00
Jason W Kim
d7c9e08b6b First steps in ARM AsmParser support for .eabi_attribute and .arch 
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146977 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 17:38:12 +00:00
Elena Demikhovsky
ba4f83b4e9 This is the second fix related to VZEXT_MOVL node. 
The failure that I see in the current version is:

LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
  0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
    0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
      0x18b9870: v4i64 = undef [ID=4]
      0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
        0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
      0x18b9970: i32 = Constant<0> [ID=3]
    0x18b9170: v2i64 = undef [ORD=1] [ID=1]
    0x18b9570: i32 = Constant<2> [ID=5]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146975 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 13:34:28 +00:00
Chandler Carruth
f2d7693fbb Begin teaching the X86 target how to efficiently codegen patterns that 
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.

The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 11:19:37 +00:00
Chandler Carruth
cfb75fba73 Fix up the CMake build for the new files added in r146960, they're 
likely to stay either way that discussion ends up resolving itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146966 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 08:42:11 +00:00
David Blaikie
2d24e2a396 Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 02:50:00 +00:00
Bob Wilson
c0b0e57a87 Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930. 
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers.  But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore.  Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early.  This also more accurately reflects
when the registers are clobbered.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146949 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 01:29:27 +00:00
Jim Grosbach
04b5d93250 ARM assembly shifts by zero should be plain 'mov' instructions. 
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.

rdar://10604663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 00:59:38 +00:00
Dan Gohman
e3376ecd50 Add basic generic CodeGen support for half. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146927 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 00:02:33 +00:00
Jim Grosbach
9b0878512f ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates. 
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"

rdar://10603913

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146925 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 23:51:07 +00:00
Jim Grosbach
2f196747f1 ARM assembly parsing and encoding support for LDRD(label). 
rdar://9932658

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 23:06:24 +00:00
Akira Hatanaka
f06cb2b207 Add patterns for matching immediates whose lower 16-bit is cleared. These 
patterns emit a single LUi instruction instead of a pair of LUi and ORi.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146900 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 20:21:18 +00:00
Akira Hatanaka
8209968306 Tidy up. Simplify logic. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146896 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:52:25 +00:00
Jim Grosbach
d22170e16a ARM NEON two-operand aliases for VPADD. 
rdar://10602276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:51:03 +00:00
Akira Hatanaka
ee973147ac Remove definitions of double word shift plus 32 instructions. Assembler or 
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146893 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:44:09 +00:00
Jim Grosbach
6849019079 ARM VFP pre-UAL mnemonic aliases for fmul[sd]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146892 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:43:50 +00:00
Akira Hatanaka
ed538b5271 Remove unused predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146889 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:32:20 +00:00
Akira Hatanaka
89dc8d790d Remove the restriction on the first operand of the add node in SelectAddr. 
This change reduces the number of instructions generated.

For example, 
(load (add (sub $n0, $n1), (MipsLo got(s))))

results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)

Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146888 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:28:37 +00:00
Jim Grosbach
9c39789c36 ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146887 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:02:41 +00:00
Jim Grosbach
61b74b4247 ARM NEON implied destination aliases for VMAX/VMIN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 18:57:38 +00:00
Jim Grosbach
eeaf1c1636 ARM NEON relax parse time diagnostics for alignment specifiers. 
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 18:31:43 +00:00
Jim Grosbach
3346dcef02 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146882 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 18:11:17 +00:00
Jakob Stoklund Olesen
9897c622e0 Remove a register class that can just as well be synthesized. 
Add the new TableGen register class synthesizer feature to the release
notes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146875 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 16:53:40 +00:00
Jakob Stoklund Olesen
570f9a972e Emit a getMatchingSuperRegClass() implementation for every target. 
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().

Delete the old manual, error-prone implementations in the targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 16:53:34 +00:00
Benjamin Kramer
0581ed792b Another variadics tweak. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146852 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-18 20:51:31 +00:00
Benjamin Kramer
2ea4cdb81f Use the fancy new VariadicFunction template instead of a plain variadic function. 
Some compilers were complaining about passing StringRef to it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146850 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-18 19:59:20 +00:00
Benjamin Kramer
4c1ea552c5 Hexagon: Remove unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146846 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-18 12:00:09 +00:00
Craig Topper
ab44d3cf49 Remove an unused X86ISD node type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146833 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 19:16:44 +00:00
Benjamin Kramer
e6cddb77dc X86: Factor the bswap asm matching to be slightly less horrible to read. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146831 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 14:36:05 +00:00
Evan Cheng
b16db81719 Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146805 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 01:25:34 +00:00
Rafael Espindola
8f7d12ccfd Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the 
asm parsing and testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 01:14:52 +00:00
Lang Hames
8b99c1e42c Make sure that the lower bits on the VSELECT condition are properly set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146800 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 01:08:46 +00:00
Jakob Stoklund Olesen
2027379985 Preserve more memory operands in ARMExpandPseudo. 
I don't think this affects anything but verbose assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146787 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 00:07:02 +00:00
Jakob Stoklund Olesen
b076fb7762 Fix off-by-one error in bucket sort. 
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.

<rdar://problem/10594653>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146767 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 23:00:05 +00:00
Jakob Stoklund Olesen
f9aabb8f32 Don't adjust for alignment padding in OffsetIsInRange. 
This adjustment is already included in the block offsets computed by
BasicBlockInfo, and adjusting again here can cause the pass to loop.

When CreateNewWater splits a basic block, OffsetIsInRange would reject
the new CPE on the next pass because of the too conservative alignment
adjustment. This caused the block to be split again, and so on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146751 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 19:10:00 +00:00
Benjamin Kramer
903456245b Hexagon: Fix a nasty order-of-initialization bug. 
Reenable the tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146750 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 19:08:59 +00:00
Jakob Stoklund Olesen
f5bb45f895 Note ARM constant island alignment in the release notes. 
The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 16:07:41 +00:00
Craig Topper
94438ba538 Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 08:06:31 +00:00
NAKAMURA Takumi
46209476e7 Target/Hexagon: Fix CMake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146724 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 06:21:02 +00:00