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224 Commits

Author SHA1 Message Date
Vincent Lejeune
4fb224e3bd R600: Always use texture cache for compute shaders 
This will improve the performance of memory reads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180762 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:14:44 +00:00
Vincent Lejeune
2c836f84db R600: use native for alu 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180761 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:14:38 +00:00
Vincent Lejeune
25f259cde2 R600: Packetize instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180760 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:14:27 +00:00
Vincent Lejeune
abcde265b1 R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:14:17 +00:00
Vincent Lejeune
e332e3559b R600: Add a Bank Swizzle operand 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180758 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:14:08 +00:00
Vincent Lejeune
7097b1ddea R600: Take inner dependency into tex/vtx clauses 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180757 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:14:00 +00:00
Vincent Lejeune
b6379de427 R600: Turn TEX/VTX into native instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180756 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:13:53 +00:00
Vincent Lejeune
631591e6f3 R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions 
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:13:39 +00:00
Vincent Lejeune
0dc415cf28 R600: Add some new processor variants 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180753 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:13:27 +00:00
Vincent Lejeune
8723c9ebf5 R600: Clean up instruction class definitions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180752 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:13:20 +00:00
Vincent Lejeune
86cdb70417 R600: config section now reports use of killgt 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180751 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:13:13 +00:00
Tom Stellard
d8b2da1136 R600: Use correct CF_END instruction on Northern Island GPUs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180735 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-29 22:23:58 +00:00
Tom Stellard
015f586bc9 R600: Fix encoding of CF_END_{EG, R600} instructions 
The EOP bit was not being encoded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180734 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-29 22:23:54 +00:00
Tom Stellard
99d8179a9b R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE 
We need to intialize this to something and since clang does not set
the shader type attribute and clang is used only for compute shaders,
initializing it to COMPUTE seems like the best choice.

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180620 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-26 18:32:24 +00:00
Tom Stellard
aa6deab608 R600: Initialize BooleanVectorContents 
Fixes test/CodeGen/R600/setcc.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180231 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-24 23:56:18 +00:00
Tom Stellard
87cba4a4c1 R600: Use SHT_PROGBITS for the .AMDGPU.config section 
The libelf implementation that is distributed here:
http://www.mr511.de/software/english.html
will not parse sections that are marked SHT_NULL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180230 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-24 23:56:14 +00:00
Vincent Lejeune
2a74639bc7 R600: Use .AMDGPU.config section to emit stacksize 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180124 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 17:34:12 +00:00
Vincent Lejeune
7a28d8afa7 R600: Add CF_END 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180123 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 17:34:00 +00:00
Matt Arsenault
9a0e12a6ed Remove unused DwarfSectionOffsetDirective string 
The value isn't actually used, and setting it emits a COFF specific
directive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180064 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-22 22:49:11 +00:00
Michael Liao
2a8bea7a8e ArrayRefize getMachineNode(). No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 22:22:57 +00:00
Tom Stellard
48b809e6e5 R600: Add pattern for the BFI_INT instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179830 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 02:11:06 +00:00
Tom Stellard
ae2a8929d8 R600/SI: Use InstFlag for VOP3 modifier operands 
InstFlag has a default value of 0 and will simplify the VOP3 patterns.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179829 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 02:11:00 +00:00
Vincent Lejeune
26ebd7aafc R600: Make Export Instruction not duplicable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179686 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-17 15:17:39 +00:00
Vincent Lejeune
58df169e82 R600: Export is emitted as a CF_NATIVE inst 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179685 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-17 15:17:32 +00:00
Vincent Lejeune
141ca7fc64 R600: Emit used GPRs count 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179684 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-17 15:17:25 +00:00
Tom Stellard
9a256300f8 R600/SI: Emit config values in register value pairs. 
Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-15 17:51:35 +00:00
Tom Stellard
bf1efe6421 R600/SI: Emit configuration value in the .AMDGPU.config ELF section 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179545 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-15 17:51:30 +00:00
Tom Stellard
3a63bf27c5 R600: Emit ELF formatted code rather than raw ISA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179544 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-15 17:51:21 +00:00
NAKAMURA Takumi
4eb5f18956 R600ControlFlowFinalizer.cpp: Fix a warning. [-Wunused-variable] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179263 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-11 04:16:27 +00:00
NAKAMURA Takumi
e7a040f9ab Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179262 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-11 04:16:22 +00:00
Michel Danzer
b187f8cd1c R600/SI: Add pattern for AMDGPUurecip 
21 more little piglits with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179186 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-10 17:17:56 +00:00
Vincent Lejeune
daefc0f9c8 R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179174 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-10 13:29:20 +00:00
Christian Konig
4d0e8a8a3e R600/SI: dynamical figure out the reg class of MIMG 
Depending on the number of bits set in the writemask.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179166 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-10 08:39:16 +00:00
Christian Konig
84a775d8e3 R600/SI: adjust writemask to only the used components 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179165 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-10 08:39:08 +00:00
Christian Konig
9c210dabda R600/SI: remove image sample writemask 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179164 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-10 08:39:01 +00:00
Vincent Lejeune
bd7c634ab9 R600: Control Flow support for pre EG gen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179020 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-08 13:05:49 +00:00
Tom Stellard
17ea10cb79 R600/SI: Add support for buffer stores v2 
v2:
  - Use the ADDR64 bit

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178931 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-05 23:31:51 +00:00
Tom Stellard
e340b7728a R600/SI: Use same names for corresponding MUBUF operands and encoding fields 
The code emitter knows how to encode operands whose name matches one of
the encoding fields.  If there is no match, the code emitter relies on
the order of the operand and field definitions to determine how operands
should be encoding.  Matching by order makes it easy to accidentally break
the instruction encodings, so we prefer to match by name.

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178930 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-05 23:31:44 +00:00
Tom Stellard
99eb040c02 R600: Add RV670 processor 
This is an R600 GPU with double support.

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178929 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-05 23:31:40 +00:00
Tom Stellard
2a4d3e7e87 R600/SI: Add processor types for each SI variant 
Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178928 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-05 23:31:35 +00:00
Tom Stellard
2fc7443498 R600/SI: Avoid generating S_MOVs with 64-bit immediates v2 
SITargetLowering::analyzeImmediate() was converting the 64-bit values
to 32-bit and then checking if they were an inline immediate.  Some
of these conversions caused this check to succeed and produced
S_MOV instructions with 64-bit immediates, which are illegal.

v2:
  - Clean up logic

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178927 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-05 23:31:20 +00:00
Vincent Lejeune
af6f407432 R600: Use a mask for offsets when encoding instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178763 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-04 14:00:09 +00:00
Vincent Lejeune
51f7225f55 R600: Fix wrong address when substituting ENDIF 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178762 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-04 14:00:03 +00:00
Vincent Lejeune
39cd6fae34 R600: Take export into account when computing cf address 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178761 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-04 13:59:59 +00:00
Vincent Lejeune
5417223f98 R600: Fix last ALU of a clause being emitted in a separate clause 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178675 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-03 18:24:47 +00:00
Vincent Lejeune
dae2a20a56 R600: Factorize maximum alu per clause in a single location 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178667 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-03 16:49:34 +00:00
Vincent Lejeune
375d767b54 R600: Simplify data structure and add DEBUG to R600ControlFlowFinalizer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178665 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-03 16:24:09 +00:00
Vincent Lejeune
795ecc3669 R600: Consider KILLGT as an ALU instruction 
Mesa does not override llvm behavior wrt KILLGT anymore so llvm
has to handle KILLGT on its own.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178664 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-03 16:24:04 +00:00
NAKAMURA Takumi
8d9594fe92 Target/R600: Fix CMake build to add missing files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178508 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-01 22:05:58 +00:00
Vincent Lejeune
08001a5a15 R600: Add support for native control flow 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178505 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-01 21:48:05 +00:00