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Commit Graph

241 Commits

Author SHA1 Message Date
Michael Liao
b118a073d7 Re-work X86 code generation of atomic ops with spin-loop
- Rewrite/merge pseudo-atomic instruction emitters to address the
  following issue:
  * Reduce one unnecessary load in spin-loop

    previously the spin-loop looks like

        thisMBB:
        newMBB:
          ld  t1 = [bitinstr.addr]
          op  t2 = t1, [bitinstr.val]
          not t3 = t2  (if Invert)
          mov EAX = t1
          lcs dest = [bitinstr.addr], t3  [EAX is implicit]
          bz  newMBB
          fallthrough -->nextMBB

    the 'ld' at the beginning of newMBB should be lift out of the loop
    as lcs (or CMPXCHG on x86) will load the current memory value into
    EAX. This loop is refined as:

        thisMBB:
          EAX = LOAD [MI.addr]
        mainMBB:
          t1 = OP [MI.val], EAX
          LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
          JNE mainMBB
        sinkMBB:

  * Remove immopc as, so far, all pseudo-atomic instructions has
    all-register form only, there is no immedidate operand.

  * Remove unnecessary attributes/modifiers in pseudo-atomic instruction
    td

  * Fix issues in PR13458

- Add comprehensive tests on atomic ops on various data types.
  NOTE: Some of them are turned off due to missing functionality.

- Revise tests due to the new spin-loop generated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164281 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20 03:06:15 +00:00
Manman Ren
127eea87d6 X86 Peephole: fold loads to the source register operand if possible.
Add more comments and use early returns to reduce nesting in isLoadFoldable.
Also disable folding for V_SET0 to avoid introducing a const pool entry and
a const pool load.

rdar://10554090 and rdar://11873276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02 19:37:32 +00:00
Manman Ren
d7d003c2b7 X86 Peephole: fold loads to the source register operand if possible.
Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.

This patch is a rework of r160919 and was tested on clang self-host on my local
machine.

rdar://10554090 and rdar://11873276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02 00:56:42 +00:00
Manman Ren
e8b4a4a9d1 Revert r160920 and r160919 due to dragonegg and clang selfhost failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160927 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-29 02:44:09 +00:00
Manman Ren
0eb3edea9c X86 Peephole: fold loads to the source register operand if possible.
Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.

rdar://10554090 and rdar://11873276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-28 16:48:01 +00:00
Manman Ren
2af66dc51a X86: peephole optimization to remove cmp instruction
For each Cmp, we check whether there is an earlier Sub which make Cmp
redundant. We handle the case where SUB operates on the same source operands as
Cmp, including the case where the two source operands are swapped.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06 17:36:20 +00:00
Jakob Stoklund Olesen
59bde4d8a1 Add early if-conversion support to X86.
Implement the TII hooks needed by EarlyIfConversion to create cmov
instructions and estimate their latency.

Early if-conversion is still not enabled by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159695 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04 00:09:58 +00:00
Craig Topper
f318457547 Make helper method static since it doesn't use anything in the class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159071 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23 04:58:41 +00:00
Manman Ren
2afde7782d Revert r157755.
The commit is intended to fix rdar://11540023.
It is implemented as part of peephole optimization. We can actually implement
this in the SelectionDAG lowering phase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06 23:53:03 +00:00
Manman Ren
c73ea9102b Revert r157831
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157896 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 03:14:24 +00:00
Manman Ren
73c2f7f5ed X86: peephole optimization to remove cmp instruction
This patch will optimize the following:
  sub r1, r3
  cmp r3, r1 or cmp r1, r3
  bge L1
TO
  sub r1, r3
  bge L1 or ble L1

If the branch instruction can use flag from "sub", then we can eliminate
the "cmp" instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157831 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01 19:49:33 +00:00
Craig Topper
241c15ffaa Remove a trailing space and fix a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157801 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01 05:34:01 +00:00
Manman Ren
91c5346d91 X86: replace SUB with CMP if possible
This patch will optimize the following
        movq    %rdi, %rax
        subq    %rsi, %rax
        cmovsq  %rsi, %rdi
        movq    %rdi, %rax
to
        cmpq    %rsi, %rdi
        cmovsq  %rsi, %rdi
        movq    %rdi, %rax

Perform this optimization if the actual result of SUB is not used.

rdar: 11540023


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31 17:20:29 +00:00
Elena Demikhovsky
177cf1e1a3 Added FMA3 Intel instructions.
I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31 09:20:20 +00:00
Craig Topper
79aa3417eb Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17 18:46:09 +00:00
Jia Liu
31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 12:03:15 +00:00
Jakob Stoklund Olesen
c2ecf3efbf Break false dependencies before partial register updates.
Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.

The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.

The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144602 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 01:15:30 +00:00
Jakob Stoklund Olesen
92fb79b7a6 Expand the x86 V_SET0* pseudos right after register allocation.
This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 05:10:54 +00:00
Jakob Stoklund Olesen
98e933f9ad Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.
I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass.  They are essentially doing the same
thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140652 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 22:57:18 +00:00
Bruno Cardoso Lopes
cbf479df8a * Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.

* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }

* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.

* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.

* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).

Patch by David Meyer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:35:57 +00:00
Jakob Stoklund Olesen
2df3f58a0b Hoist hasLoadFromStackSlot and hasStoreToStackSlot.
These the methods are target-independent since they simply scan the
memory operands.  They can live in TargetInstrInfoImpl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 20:53:24 +00:00
Evan Cheng
8c3fee5903 Refactor X86 target to separate MC code from Target code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135930 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 18:43:53 +00:00
Evan Cheng
4db3cffe94 Hide the call to InitMCInstrInfo into tblgen generated ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 17:57:27 +00:00
Francois Pichet
1b47720391 Remove unused OpcodeMask enumerator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 17:02:53 +00:00
Francois Pichet
d9e57c146d Fix MSVC warning: "is out of range for enum constant"
MSVC doesn't support 64 bit enum. 
OpcodeMask is not used anywhere in the code base.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 15:58:10 +00:00
Chris Lattner
7a2bdde0a0 Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 05:18:47 +00:00
Joerg Sonnenberger
c15a91dfc8 Make OpcodeMask an unsigned long long literal to deal with overflow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 21:38:17 +00:00
Joerg Sonnenberger
4a8ac8de1d Add support for the VIA PadLock instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 16:58:13 +00:00
Joerg Sonnenberger
229e4523f2 Expand Op0Mask by one bit in preparation for the PadLock prefixes.
Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128822 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 15:58:30 +00:00
Andrew Trick
e0ef509aeb Increased the register pressure limit on x86_64 from 8 to 12
regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.

Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.

Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127067 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 08:00:22 +00:00
Andrew Trick
8d4a422513 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 06:31:54 +00:00
Rafael Espindola
87ca0e077d Implement xgetbv and xsetbv.
Patch by Jai Menon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126165 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22 00:35:18 +00:00
Anton Korobeynikov
cd775ceff0 Move callee-saved regs spills / reloads to TFI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120228 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27 23:05:03 +00:00
Chris Lattner
21d272874b tidy up, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119092 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 23:32:42 +00:00
Evan Cheng
2312842de0 Re-enable register pressure aware machine licm with fixes. Hoist() may have
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 18:58:51 +00:00
Daniel Dunbar
9869413802 Revert r116781 "- Add a hook for target to determine whether an instruction def
is", which breaks some nightly tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116816 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 17:14:24 +00:00
Evan Cheng
11e8b74a7a - Add a hook for target to determine whether an instruction def is
"long latency" enough to hoist even if it may increase spilling. Reloading
  a value from spill slot is often cheaper than performing an expensive
  computation in the loop. For X86, that means machine LICM will hoist
  SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
  instructions.
- Enable register pressure aware machine LICM by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:55:07 +00:00
Chris Lattner
45a1cb26a3 Reduce casting in various tables by defining the table
with the right types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:08:41 +00:00
Chris Lattner
548abfcbd6 Implement support for the bizarre 3DNow! encoding (which is unlike anything
else in X86), and add support for pavgusb.  This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.

If someone else is interested in banging out the rest of the 3DNow! 
instructions, it should be quite easy now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 18:08:05 +00:00
Chris Lattner
40cc3f8783 fix rdar://8444631 - encoder crash on 'enter'
What a weird instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114190 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:02:29 +00:00
Chris Lattner
beac75da37 implement rdar://6653118 - fastisel should fold loads where possible.
Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:

int foo(int x, int y, int z) {
  return x+y+z;
}

used to compile into:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	movl	4(%rsp), %esi
	addl	%edx, %esi
	movl	(%rsp), %edx
	addl	%esi, %edx
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Now we produce:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	addl	4(%rsp), %edx    ## Folded load
	addl	(%rsp), %edx     ## Folded load
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Fewer instructions and less register use = faster compiles.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-05 02:18:34 +00:00
Bruno Cardoso Lopes
e943c15621 Fix PR7748 without using microsoft extensions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112128 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 01:02:53 +00:00
Chris Lattner
59f8a6a666 fix PR7465, mishandling of lcall and ljmp: intersegment long
call and jumps.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 01:18:43 +00:00
Chris Lattner
134d8eec87 remove the JIT "NeedsExactSize" feature and supporting logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 21:17:55 +00:00
Chris Lattner
456fdaf0ce instead of migrating it to the MC instruction encoder, just
rip out the implementation of X86InstrInfo::GetInstSizeInBytes.
The code being ripped out just implemented a copy and hacked up
version of the (old) instruction encoder, and is buggy and 
terrible in other ways.  Since "GetInstSizeInBytes" is really 
only there to support the JIT's "NeedsExactSize" hook (which
noone is using), just rip out the code.  I will rip out the
NeedsExactSize hook next.

This resolves rdar://7617809 - switch X86InstrInfo::GetInstSizeInBytes to use X86MCCodeEmitter



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 21:05:13 +00:00
Jakob Stoklund Olesen
78e6e00922 Remove the isMoveInstr() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 22:35:46 +00:00
Bruno Cardoso Lopes
87a85c7ef0 AVX 256-bit conversion instructions
Add the x86 VEX_L form to handle special cases where VEX_L must be set.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108274 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 21:07:28 +00:00
Jakob Stoklund Olesen
4ea8771535 X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108076 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 05:44:30 +00:00
Bruno Cardoso Lopes
be95c15903 Merge VEX enums with other x86 enum forms. Also fix all checks of which VEX
fields to use. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 01:56:45 +00:00
Chris Lattner
ac0ed5dc08 add some long-overdue enums to refer to the parts of the 5-operand
X86 memory operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107925 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:41:28 +00:00