Duncan Sands
f7331b3dd7
Fold the adjust_trampoline intrinsic into
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init_trampoline. There is now only one
trampoline intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41841 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-11 14:10:23 +00:00
Evan Cheng
be36798bfe
80 col.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41812 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-10 22:22:23 +00:00
Chris Lattner
bf8ae84a21
Add some notes about better flag handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41808 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-10 21:43:18 +00:00
Owen Anderson
718cb665ca
Add lengthof and endof templates that hide a lot of sizeof computations.
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Patch by Sterling Stein!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-07 04:06:50 +00:00
Dale Johannesen
eaf089430e
Enhance APFloat to retain bits of NaNs (fixes oggenc).
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Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41632 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-31 04:03:46 +00:00
Raul Herbster
8c132633c8
Instruction formats added used to generate multiply instructions of V5TE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41629 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-30 23:34:14 +00:00
Raul Herbster
b94e60872e
Unused relocation type reloc_arm_absolute removed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41628 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-30 23:31:35 +00:00
Raul Herbster
9c1a3827ce
Comments added. It now generates V5TE multiply instructions. However, it is still necessary to model PUWLSH bits more clearly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41627 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-30 23:29:26 +00:00
Raul Herbster
37fb5b154c
ARM instruction table was modified by adding information to generate multiply instruction of V5TE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41626 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-30 23:25:47 +00:00
Raul Herbster
d05c04c169
JITInfo now resolves function addrs and also relocations. It always emits a stub.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41625 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-30 23:21:27 +00:00
Evan Cheng
35b35c5c32
Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41597 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-30 05:52:20 +00:00
Evan Cheng
0ff94f7fcc
Initial JIT support for ARM by Raul Fernandes Herbster.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-07 01:37:15 +00:00
Dan Gohman
61e729e2e9
More explicit keywords.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40757 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-02 21:21:54 +00:00
Evan Cheng
7fc77611ef
Indexed loads each has 2 outputs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40658 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-01 00:12:08 +00:00
Dan Gohman
f452207d20
More explicit keywords.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40589 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-30 14:51:59 +00:00
Duncan Sands
36397f5034
Support for trampolines, except for X86 codegen which is
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still under discussion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-27 12:58:54 +00:00
Dan Gohman
b8275a3f6f
Don't ignore the return value of AsmPrinter::doInitialization and
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AsmPrinter::doFinalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40487 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-25 19:33:14 +00:00
Evan Cheng
ffbaccae02
No more noResults.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-21 00:34:19 +00:00
Evan Cheng
8bd6035750
Added -print-emitted-asm to print out JIT generated asm to cerr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40123 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-20 21:56:13 +00:00
Evan Cheng
64d80e3387
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
Evan Cheng
4558b807a2
Only adjust esp around calls in presence of alloca.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40030 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 00:42:58 +00:00
Chris Lattner
c3dbe70ce7
no email addrs in file headers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39962 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-17 05:56:43 +00:00
Anton Korobeynikov
2365f51ed0
Long live the exception handling!
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This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-14 14:06:15 +00:00
Dale Johannesen
66a2a8f878
ARM: make branch folder remove unconditional branches
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following jump tables that it earlier inserted. This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39782 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-12 16:45:35 +00:00
Dale Johannesen
5d9c4b6020
Fix hang compiling TimberWolf (allow for islands
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of size other than 4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39743 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-11 18:32:38 +00:00
Evan Cheng
8202010364
Didn't mean the last commit. Revert.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38515 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-10 22:00:16 +00:00
Evan Cheng
c608ff22e7
Update.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38513 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-10 21:49:47 +00:00
Evan Cheng
13ab020ea0
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-10 18:08:01 +00:00
Chris Lattner
87bdba6d6a
The various "getModuleMatchQuality" implementations should return
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zero if they see a target triple they don't understand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38463 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-09 17:25:29 +00:00
Evan Cheng
9ad6f03166
No need for ccop anymore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37965 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 23:34:09 +00:00
Evan Cheng
4b9cb7d135
Incorrect check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37962 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 23:23:19 +00:00
Evan Cheng
06aae67b83
Do away with ImmutablePredicateOperand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37961 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 23:22:46 +00:00
Evan Cheng
dfb2ebac29
Print the s bit if the instruction is toggled to its CPSR setting form.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37932 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 01:01:34 +00:00
Evan Cheng
04c813d00c
PredicateDefOperand -> OptionalDefOperand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37931 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 01:00:49 +00:00
Evan Cheng
148b6a419f
Initial ARM JIT support by Raul Fernandes Herbster.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37926 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 21:15:40 +00:00
Evan Cheng
d54874a06d
Unbreak the build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37914 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 17:13:19 +00:00
Gabor Greif
a99be51bf5
Here is the bulk of the sanitizing.
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Almost all occurrences of "bytecode" in the sources have been eliminated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37913 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 17:07:56 +00:00
Evan Cheng
0e1d37904a
Reflects the chanegs made to PredicateOperand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37898 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:18:20 +00:00
Evan Cheng
16b6598325
Added ARM::CPSR to represent ARM CPSR status register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37897 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:17:13 +00:00
Evan Cheng
ee568cf794
Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37896 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:15:27 +00:00
Evan Cheng
c85e832eb7
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37895 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:13:32 +00:00
Evan Cheng
3b5b8368f3
Added ARM::CPSR to represent ARM CPSR status register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37894 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:11:03 +00:00
John Criswell
e644ef7b09
Convert .cvsignore files
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37801 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-29 16:35:07 +00:00
Evan Cheng
e2446c6076
Silence a warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37737 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-26 18:31:22 +00:00
Dan Gohman
d45eddd214
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-26 00:48:07 +00:00
Owen Anderson
0819a9d386
Fix the build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37705 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-22 16:59:54 +00:00
Dan Gohman
ea859be53c
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
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TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-22 14:59:07 +00:00
Dale Johannesen
5411835165
Quote complex names for Darwin X86 and ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37700 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-22 00:54:56 +00:00
Evan Cheng
97e604e7d8
Be more conservative of duplicating blocks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37669 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 23:55:02 +00:00
Evan Cheng
277f0741c5
Allow predicated immediate ARM to ARM calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37659 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 21:05:09 +00:00