Commit Graph

94766 Commits

Author SHA1 Message Date
Alexey Samsonov
e393b73808 Fix dereferencing end iterator in SimplifyCFG. Patch by Ye Mei.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187646 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-02 08:06:43 +00:00
NAKAMURA Takumi
ee1d7db74b Revert r187597, "Bugfix for making the DWARF debug strings and labels to code emitted as secrel32 instead of long opcodes (only for coff). This makes them debuggable with GDB."
It broke x86_64-win32 builder in llvm/test/DebugInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187642 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-02 03:46:05 +00:00
Eric Christopher
9f4eaaf0dc Use @rpath for libraries rather than @executable_path on OSX.
Patch by Benjamin Scarlet!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-02 01:51:52 +00:00
Eric Christopher
be9f508aec Temporarily revert "Debug Info Finder|Verifier: handle DbgLoc attached to
instructions." in an attempt to bring back some bots.

This reverts commit r187609.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187638 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-02 00:49:44 +00:00
Matt Arsenault
7eef3bdd7b Teach InstructionSimplify about pointer address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187635 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-02 00:10:44 +00:00
Akira Hatanaka
ddbdeefa28 [mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,
remove lines that are setting DecoderNamespace for pseudo atomic instructions.

No intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187632 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 23:14:16 +00:00
Matt Arsenault
186f8f9d41 Teach getOrEnforceKnownAlignment about address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187629 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 22:42:18 +00:00
Nadav Rotem
72bc423e7f Move the optlevel check to the frontend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187628 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 22:41:58 +00:00
Carlo Kok
cfe855d658 fix for LLVM debug info on llvm-mips-linux where the label name uses % instead of L as a prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187623 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 22:15:34 +00:00
Bill Wendling
61fc8d670f Use function attributes to indicate that we don't want to realign the stack.
Function attributes are the future! So just query whether we want to realign the
stack directly from the function instead of through a random target options
structure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187618 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 21:42:05 +00:00
Rafael Espindola
8cb1d81250 Expose that the unique file ID has a device and a file component.
The use of sd_dev and st_ino has reached libclang, so expose the two components
in UniqueID so that we can use it in clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187616 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 21:36:02 +00:00
Daniel Malea
44c8e346c7 Fixed the Intel-syntax X86 disassembler to respect the (existing) option for hexadecimal immediates, to match AT&T syntax. This also brings a new option for C-vs-MASM-style hex.
Patch by Richard Mitton
Reviewed: http://llvm-reviews.chandlerc.com/D1243



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187614 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 21:18:16 +00:00
Reed Kotler
b1fa7d4d26 Fix some issues with Mips16 floating when certain intrinsics are present.
This is actually an LLVM bug in the way it generates signatures for these
when soft float is enabled. For example, floor ends up having the signature
of int64(int64). The signature part is not the same as where the actual
parameter types are recorded, and those ARE of course int64(int64) when
soft float is enabled. (Yes, Mips16 hard float uses soft float but with
different runtime rounes but then has to interoperate with Mips32 using
normal floating point). This logic will eventually be moved to the 
Mips16HardFloat pass so it's not worth sorting out these issues in LLVM
since nobody but Mips16 cares about these signatures, as far as I know,
and even I won't eventually either.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187613 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 21:17:53 +00:00
Carlo Kok
e18804ecd0 ARM/Hexagon testcases can't compile x86 only testcase. Reverting change to testcase & fixing check for all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187610 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 20:53:57 +00:00
Manman Ren
f589eef864 Debug Info Finder|Verifier: handle DbgLoc attached to instructions.
Also remove checking of llvm.dbg.sp since it is not used in generating dwarf.

Current state of Finder:
DebugInfoFinder tries to list all debug info MDNodes used in a module. To
list debug info MDNodes used by an instruction, DebugInfoFinder provides
processDeclare, processValue and processLocation to handle DbgDeclareInst,
DbgValueInst and DbgLoc attached to instructions. processModule will go
through all DICompileUnits in llvm.dbg.cu and list debug info MDNodes
used by the CUs.

TODO:
1> Finder has a list of CUs, SPs, Types, Scopes and global variables. We
need to add a list of variables that are used by DbgDeclareInst and
DbgValueInst.
2> MDString fields should be null or isa<MDString> and MDNode fields should be
null or isa<MDNode>. We currently use empty string or int 0 to represent null.
3> Go though Verify functions and make sure that they check field types.
4> Clean up existing testing cases to remove llvm.dbg.sp and make sure each
testing case has a llvm.dbg.cu.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187609 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 20:52:39 +00:00
David Blaikie
c8b93557da DebugInfo: Emit definitions for types with no members.
The absence of members was a poor/incorrect proxy for "is definition".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187607 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 20:30:22 +00:00
Carlo Kok
70cf72e092 change the inlinefnlocalvar testcase so it uses a triple that's not coff (doesn't seem to matter for the testcase itself, what it tests isn't triple specific), as coff has a slightly different way of emitting what it checks for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187604 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 20:17:37 +00:00
Bob Wilson
c8c344b26e Temporarily xfail a test that breaks on OS X when building with LTO.
This is another case where internalize hides a symbol that is needed by
a loadable module.  I am currently investigating a proper fix but this patch
will get our buildbot to pass in the meantime. <rdar://problem/14578094>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187601 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 19:29:26 +00:00
Sean Silva
2b61eb9843 Update incorrect file headers.
One of these was spotted in review by Rafael.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187598 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 18:42:28 +00:00
Carlo Kok
5b25082ddb Bugfix for making the DWARF debug strings and labels to code emitted as secrel32 instead of long opcodes (only for coff). This makes them debuggable with GDB.
fixes Bug 16249 - LLVM generates broken debug info on Windows 

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187597 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 18:38:14 +00:00
Nadav Rotem
a4cbd78af8 Only enable SLP-vectorization on O3 builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187595 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 18:28:15 +00:00
Simon Atanasyan
df263de386 Pass -G argument to cmake with the same generator's name as used for the
initial cmake invocation.

Patch reviewed by Reid Kleckner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187591 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 18:04:07 +00:00
Robert Lytton
4da77f8d5f remove executable permission from IntrinsicsXCore.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187584 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 17:17:59 +00:00
Tom Stellard
692ee102eb R600: Add 64-bit float load/store support
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions

Tom Stellard:
  - Mark vec2 operations as expand.  The addition of a vec2 register
    class made them all legal.

Patch by: Dmitry Cherkassov

Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 15:23:42 +00:00
Tom Stellard
98b357e1cd R600: Use 64-bit alignment for 64-bit kernel arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187581 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 15:23:31 +00:00
Tom Stellard
8cd70d3a5b R600/SI: Custom lower i64 ZERO_EXTEND
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 15:23:26 +00:00
Elena Demikhovsky
0780179d53 EVEX and compressed displacement encoding for AVX512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187576 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 13:34:06 +00:00
Richard Sandiford
8f0ad5ae8f [SystemZ] Reuse CC results for integer comparisons with zero
This also fixes a bug in the predication of LR to LOCR: I'd forgotten
that with these in-place instruction builds, the implicit operands need
to be added manually.  I think this was latent until now, but is tested
by int-cmp-45.c.  It also adds a CC valid mask to STOC, again tested by
int-cmp-45.c.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187573 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 10:39:40 +00:00
Richard Sandiford
3237f88882 [SystemZ] Prefer comparisons with zero
Convert >= 1 to > 0, etc.  Using comparison with zero isn't a win on its own,
but it exposes more opportunities for CC reuse (the next patch).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187571 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 10:29:45 +00:00
Vladimir Medic
a701de8d24 Add tests for Mips DSP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187570 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 09:35:25 +00:00
Vladimir Medic
588f408b95 Moving definition of MnemonicContainsDot field from class Instruction to class AsmParser as suggested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 09:25:27 +00:00
Tim Northover
87773c318f AArch64: add initial NEON support
Patch by Ana Pazos.

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 09:20:35 +00:00
Robert Lytton
691aa094da XCore target: add GCCBuiltin to four intrinsics
The following are made available by clang in the XCore ABI
	__builtin_bitrev
	__builtin_getid
	__builtin_getps
	__builtin_setps

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187566 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 08:41:32 +00:00
Robert Lytton
dd1cfe2129 XCore target: Fix Vararg handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187565 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 08:29:44 +00:00
Robert Lytton
f2617291e3 XCore target: Add byval handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187563 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 08:18:55 +00:00
Robert Lytton
98369fb0e7 Xcore target
Fix emitArrayBound() calling OutStreamer.Emit*() multiple times when trying to print a single line

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187562 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 07:52:05 +00:00
Reed Kotler
f71698747e Fix some misc. issues with Mips16 fp stubs.
1) They should never be inlined.
2) A naming inconsistency with gcc mips16
3) Stubs should not have the global attribute



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187555 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 02:26:31 +00:00
Eric Christopher
9d45f914f0 Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187554 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 01:38:16 +00:00
Reed Kotler
d49475bebc Add an omitted IsCall=1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187553 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 00:59:06 +00:00
Hans Wennborg
a15d5db7f2 Option parsing: remove non-SUPPORT_ALIASARGS fall-back
The clients of this code have been updated to all support AliasArgs.

This depends on Clang r187538 and lld r187541.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 23:28:51 +00:00
Hans Wennborg
9dd8c0cffe Option parsing: add support for alias arguments.
This makes option aliases more powerful by enabling them to
pass along arguments to the option they're aliasing.

For example, if we have a joined option "-foo=", we can now
specify a flag option "-bar" to be an alias of that, with the
argument "baz".

This is especially useful for the cl.exe compatible clang driver,
where many options are aliases. For example, this patch enables
us to alias "/Ox" to "-O3" (-O is a joined option), and "/WX" to
"-Werror" (again, -W is a joined option).

Differential Revision: http://llvm-reviews.chandlerc.com/D1245

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187537 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 22:44:41 +00:00
Nadav Rotem
03fb46bed1 80-col
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187535 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 22:17:45 +00:00
Andrew Trick
d3d751804c comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187531 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 21:05:54 +00:00
Kevin Enderby
e38070fc32 Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
While the .td entry is nice and all, it takes a pretty gross hack in
ARMAsmParser::ParseInstruction() because of handling of other "subs"
instructions to get it to match.  Ran it by Jim Grosbach and he said it was
about what he expected to make this work given the existing code.

rdar://14214063


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187530 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 21:05:30 +00:00
Tom Stellard
6b3f6a744a Revert "R600: Non vector only instruction can be scheduled on trans unit"
This reverts commit 98ce62780e.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 20:43:27 +00:00
Tom Stellard
5519dc9de8 Revert "TableGen: Enumerate Schedule Model too."
This reverts commit 2ca1e4a39c.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 20:43:08 +00:00
Tom Stellard
af2ea2a4fb Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"
This reverts commit 3f1de26cb5.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 20:43:03 +00:00
Vincent Lejeune
26db9ecfac R600: Do not mergevector after a vector reg is used
If we merge vector when a vector is used, it will generate an artificial
antidependency that can prevent 2 tex/vtx instructions to use the same
clause and thus generate extra clauses that reduce performance.

There is no test case as such situation is really hard to predict.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187516 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:32:12 +00:00
Vincent Lejeune
8e37705a73 R600: Avoid more than 4 literals in the same instruction group at scheduling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187515 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:32:07 +00:00
Vincent Lejeune
98ce62780e R600: Non vector only instruction can be scheduled on trans unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:31:56 +00:00