Commit Graph

87461 Commits

Author SHA1 Message Date
Tom Stellard
f98f2ce29e Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 21:25:42 +00:00
Bill Schmidt
57ac1f458a This patch implements the general dynamic TLS model for 64-bit PowerPC.
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:

     Instruction                            Relocation            Symbol
  addis ra,r2,x@got@tlsgd@ha           R_PPC64_GOT_TLSGD16_HA       x
  addi  r3,ra,x@got@tlsgd@l            R_PPC64_GOT_TLSGD16_L        x
  bl __tls_get_addr(x@tlsgd)           R_PPC64_TLSGD                x
                                       R_PPC64_REL24           __tls_get_addr
  nop
  <use address in r3>

The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation.  This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr.  Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation.  So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.

Most of the code is pretty straightforward.  I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call.  Something in the 
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations.  This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().

Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.

Comments welcome!

Thanks,
Bill


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169910 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 20:30:11 +00:00
Eric Christopher
0b944ee36f Update some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169907 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 19:42:09 +00:00
Nadav Rotem
5e9efa10fc Loop Vectorize: optimize the vectorization of trunc(induction_var). The truncation is now done on scalars.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 18:58:10 +00:00
Eli Bendersky
37a9830d20 Remove the RelaxAll overrule in MCAssembler::fixupNeedsRelaxation,
because that method is only getting called for MCInstFragment. These
fragments aren't even generated when RelaxAll is set, which is why the
flag reference here is superfluous. Removing it simplifies the code
with no harmful effects.

An assertion is added higher up to make sure this path is never
reached.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169886 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 17:16:00 +00:00
Rafael Espindola
0439f3e0cf Use an ArrayRef instead of a std::vector&.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169881 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 16:36:02 +00:00
Joel Jones
8293b7b8b1 Add comment for load folding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169880 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 16:10:25 +00:00
Dmitri Gribenko
e4b3e9445f Documentation: convert Passes.html to reST.
Since now we have an autogenerated TOC, a manually written table of all passes
was removed.

Patch by Anthony Mykhailenko with small fixes by me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169867 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 15:29:37 +00:00
NAKAMURA Takumi
f38833c7ad llvm/test/TableGen: Remove XFAIL:vg_leak in dozen of tests, according to llvm-x86_64-linux-vg_leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169862 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 13:14:16 +00:00
Evgeniy Stepanov
7fa2240485 [msan] Use explicitely aligned stores and loads with function argument shadow.
Use explicitely aligned store and load instructions to deal with argument and
retval shadow. This matters when an argument's alignment is higher than
__msan_param_tls alignment (which is the case with __m128i).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169859 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 12:34:09 +00:00
Patrik Hagglund
34525f9ac0 Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 11:14:33 +00:00
Chandler Carruth
7550f96b2f Holding my nose and moving the accumulation routine to GEPOperator
instead of the instruction. I've left a forwarding wrapper for the
instruction so users with the instruction don't need to create
a GEPOperator themselves.

This lets us remove the copy of this code in instsimplify.

I've looked at most of the other copies of similar code, and this is the
only one I've found that is actually exactly the same. The one in
InlineCost is very close, but it requires re-mapping non-constant
indices through the cost analysis value simplification map. I could add
direct support for this to the generic routine, but it seems overly
specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169853 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 11:05:15 +00:00
Chandler Carruth
4ced4ee94b Hoist the GEP constant address offset computation to a common home on
the GEP instruction class.

This is part of the continued refactoring and cleaning of the
infrastructure used by SROA. This particular operation is also done in
a few other places which I'll try to refactor to share this
implementation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169852 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 10:29:10 +00:00
Patrik Hagglund
05749cff9b Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,
instead of EVTs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 10:24:48 +00:00
Patrik Hagglund
47fd10f2fc Change TargetLowering::getTypeForExtArgOrReturn to take and return
MVTs, instead of EVTs.

Accordingly, add bitsLT (and similar) to MVT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169850 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 10:20:51 +00:00
Patrik Hagglund
1d367e9bcc Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,
from EVT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169849 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 10:16:19 +00:00
Patrik Hagglund
2d916231ff Change TargetLowering::RegisterTypeForVT to contain MVTs, instead of
EVTs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169848 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 10:09:23 +00:00
Patrik Hagglund
235c75cc21 Change TargetLowering::TransformToType to contain MVTs, instead of
EVTs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169847 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 10:05:04 +00:00
Patrik Hagglund
78a70f3c60 Change TargetLowering::getRepRegClassCostFor, getIndexedLoadAction,
getIndexedStoreAction, and addRegisterClass to take an MVT, instead
of EVT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169846 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 10:00:35 +00:00
Patrik Hagglund
bade0345d1 Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169845 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 09:57:18 +00:00
Patrik Hagglund
bb2543bb0e Change TargetLowering::getTypeToPromoteTo to take and return MVTs,
instead of EVTs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169844 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 09:54:23 +00:00
Patrik Hagglund
204301f045 Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 09:51:27 +00:00
Patrik Hagglund
aff674331e Change TargetLowering::getCondCodeAction to take an MVT, instead of
EVT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 09:48:14 +00:00
Patrik Hagglund
3166283ac1 Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169841 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 09:42:24 +00:00
Patrik Hagglund
ffa03b7981 Change TargetLowering::getLoadExtAction to take an MVT, instead of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 09:39:09 +00:00
Patrik Hagglund
968947766b Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169839 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 09:32:56 +00:00
Patrik Hagglund
aa7744d75f Change TargetLowering::getRepRegClassFor to take an MVT, instead of
EVT.

Accordingly, change RegDefIter to contain MVTs instead of EVTs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 09:31:43 +00:00
Patrik Hagglund
8163ca76f0 Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.

This is the first, in a series of patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 09:10:33 +00:00
Hao Liu
659dacd66f revert the test change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169823 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 06:25:18 +00:00
Hao Liu
7fc66a22d8 A newbie try a test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169821 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 06:22:54 +00:00
NAKAMURA Takumi
d181342eee [CMake] Remove dependencies to intrinsics_gen I introduced in r169724.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 05:53:54 +00:00
NAKAMURA Takumi
a98259eefa llvm/Target/TargetMachine.h: Remove two dependent headers.
-#include "llvm/Target/TargetTransformImpl.h"
-#include "llvm/TargetTransformInfo.h"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 05:53:43 +00:00
NAKAMURA Takumi
f2a68db426 llvm/tools: Add #include "llvm/TargetTransformInfo.h"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169817 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 05:53:37 +00:00
Jyotsna Verma
2d3b67ec0e Use multiclass for new-value store instructions with MEMri operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 05:12:25 +00:00
Nadav Rotem
cfb6285fdb Fix PR14565. Don't if-convert loops that have switch statements in them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169813 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 04:55:10 +00:00
Rafael Espindola
613abf3fa6 Change some functions to take const pointers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169812 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 03:10:43 +00:00
Evan Cheng
6a1b5cc7c6 Stylistic tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169811 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 02:31:57 +00:00
Chad Rosier
1ad9253c9d Add a triple to this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169803 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 00:51:36 +00:00
Chandler Carruth
1c49fda408 Fix a miscompile in the DAG combiner. Previously, we would incorrectly
try to reduce the width of this load, and would end up transforming:

  (truncate (lshr (sextload i48 <ptr> as i64), 32) to i32)
to
  (truncate (zextload i32 <ptr+4> as i64) to i32)

We lost the sext attached to the load while building the narrower i32
load, and replaced it with a zext because lshr always zext's the
results. Instead, bail out of this combine when there is a conflict
between a sextload and a zext narrowing. The rest of the DAG combiner
still optimize the code down to the proper single instruction:

  movswl 6(...),%eax

Which is exactly what we wanted. Previously we read past the end *and*
missed the sign extension:

  movl 6(...), %eax

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169802 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 00:36:57 +00:00
Paul Redmond
0a0990af1c move X86-specific test
This test case uses -mcpu=corei7 so it belongs in CodeGen/X86

Reviewed by: Nadav


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169801 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 00:36:43 +00:00
Bill Wendling
77f06d93b9 Fix grammar-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169798 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 00:23:07 +00:00
Chad Rosier
425e951734 Fall back to the selection dag isel to select tail calls.
This shouldn't affect codegen for -O0 compiles as tail call markers are not
emitted in unoptimized compiles.  Testing with the external/internal nightly
test suite reveals no change in compile time performance.  Testing with -O1,
-O2 and -O3 with fast-isel enabled did not cause any compile-time or
execution-time failures.  All tests were performed on my x86 machine.
I'll monitor our arm testers to ensure no regressions occur there.

In an upcoming clang patch I will be marking the objc_autoreleaseReturnValue
and objc_retainAutoreleaseReturnValue as tail calls unconditionally.  While
it's theoretically true that this is just an optimization, it's an
optimization that we very much want to happen even at -O0, or else ARC
applications become substantially harder to debug.

Part of rdar://12553082

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169796 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 00:18:02 +00:00
Eric Christopher
0e3e9b79f6 Refactor out the abbreviation handling into a separate class that
controls each of the abbreviation sets (only a single one at the
moment) and computes offsets separately as well for each set
of DIEs.

No real function change, ordering of abbreviations for the skeleton
CU changed but only because we're computing in a separate order. Fix
the testcase not to care.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169793 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10 23:34:43 +00:00
Evan Cheng
376642ed62 Some enhancements for memcpy / memset inline expansion.
1. Teach it to use overlapping unaligned load / store to copy / set the trailing
   bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies.
2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g.
   x86 and ARM.
3. When memcpy from a constant string, do *not* replace the load with a constant
   if it's not possible to materialize an integer immediate with a single
   instruction (required a new target hook: TLI.isIntImmLegal()).
4. Use unaligned load / stores more aggressively if target hooks indicates they
   are "fast".
5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8.
   Also increase the threshold to something reasonable (8 for memset, 4 pairs
   for memcpy).

This significantly improves Dhrystone, up to 50% on ARM iOS devices.

rdar://12760078


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10 23:21:26 +00:00
Arnold Schwaighofer
2b475922e6 Optimistically analyse Phi cycles
Analyse Phis under the starting assumption that they are NoAlias. Recursively
look at their inputs.
If they MayAlias/MustAlias there must be an input that makes them so.

Addresses bug 14351.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169788 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10 23:02:41 +00:00
Lang Hames
07f6a4fde0 Defer call to InitSections until after MCContext has been initialized. If
InitSections is called before the MCContext is initialized it could cause
duplicate temporary symbols to be emitted later (after context initialization
resets the temporary label counter).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169785 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10 22:49:11 +00:00
Anshuman Dasgupta
079e0819bc Fix PR14568: Avoid the DFA packetizer from making an invalid read
beyond array bounds.

No test case since I cannot reproduce an ICE with this bug. According
to Carlos -- the bug reporter -- a segfault occurs only when LLVM is
compiled with a specific version of GCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169783 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10 22:45:57 +00:00
Eric Christopher
617d18385f Rearrange vars and make comments more obvious.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169780 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10 22:25:41 +00:00
Eric Christopher
642630ef2b Remove blank line at top of file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169779 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10 22:25:38 +00:00
Eric Christopher
9171fb9cfb Fix a coding style nit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169776 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10 22:00:20 +00:00