Commit Graph

92058 Commits

Author SHA1 Message Date
Jyotsna Verma
ddcf3ee768 Reverting r181331.
Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 17:12:35 +00:00
Jyotsna Verma
81fda3b4d5 Hexagon: Fix Small Data support to handle -G 0 correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181331 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 16:42:15 +00:00
Richard Sandiford
46eb4a61c8 Mention SystemZ in the release notes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181328 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 15:52:32 +00:00
Jyotsna Verma
8cc93593cd Hexagon: Set accessSize and addrMode on all load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181324 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 15:06:29 +00:00
Michael Kuperstein
c208c43a8a Re-enable AVX detection on x64 platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181313 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 14:05:33 +00:00
Richard Sandiford
7a1ead46fb [SystemZ] Fix InitMCCodeGenInfo call
createSystemZMCCodeGenInfo was not passing the optimization level to
InitMCCodeGenInfo(), so -O0 would be ignored.  Fixes DebugInfo/namespace.ll
after the changes in r181271.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 12:56:31 +00:00
Rafael Espindola
d31ba134bb Note that EH is now supported in MCJIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181305 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 12:29:17 +00:00
Timur Iskhodzhanov
664fbee9c8 Fix the VS2010 build broken by r181271
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181296 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 07:47:47 +00:00
Tim Northover
338eba7380 Correct logical shift documentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181290 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 06:17:14 +00:00
Arnold Schwaighofer
eb95cec176 LoopVectorize: getConsecutiveVector must respect signed arithmetic
We were passing an i32 to ConstantInt::get where an i64 was needed and we must
also pass the sign if we pass negatives numbers. The start index passed to
getConsecutiveVector must also be signed.

Should fix PR15882.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181286 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 04:37:05 +00:00
David Blaikie
d2e0f7ee15 DebugInfo: Support imported modules in lexical blocks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181271 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:33:07 +00:00
Tom Stellard
3d834a44f6 R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181269 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:19 +00:00
Tom Stellard
ea73bd8a54 R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemask
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:15 +00:00
Tom Stellard
651a4c8ee0 R600/SI: Add intrinsic for texture image loading
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:12 +00:00
Tom Stellard
e756ffd888 R600/SI: Add pattern for uint_to_fp
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:07 +00:00
Tom Stellard
586862ae23 R600/SI: Add patterns for integer maxima / minima
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:04 +00:00
Tom Stellard
354769ba32 R600/SI: Add pattern for AMDGPU.trunc intrinsic
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:00 +00:00
Krzysztof Parzyszek
942940a326 Print IR from Hexagon MI passes with -print-before/after-all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181255 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:58:00 +00:00
Andrew Trick
61e0172197 Implemented public interface for modifying registered (not positional or sink options) command line options at runtime.
Patch by Dan Liew!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181254 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:56:35 +00:00
Andrew Trick
b7ad33b719 Support command line option categories.
Patch by Dan Liew!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181253 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:56:23 +00:00
Krzysztof Parzyszek
b072090f39 Cleanup of the HexagonTargetMachine setup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181250 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:25:45 +00:00
David Majnemer
8ec23cb07e InstCombine: (X ^ signbit) + C -> X + (signbit ^ C)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181249 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:21:31 +00:00
Eric Christopher
e305e03d6f Hoist boundary condition out of loop header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181248 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:19:44 +00:00
Eric Christopher
5a0c366b1f Untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181247 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:19:41 +00:00
Bill Wendling
d87dceb8d6 Reduce attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181245 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 20:57:23 +00:00
Rafael Espindola
7098ae2fee Split Alignment out of the Section Characteristics.
The alignment is just a byte in the middle of Characteristics, not an
independent flag. Making it an independent field in the yaml
representation makes it more yamlio friendly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181243 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 20:11:21 +00:00
Jyotsna Verma
1a7eab3878 Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 18:49:23 +00:00
Jean-Luc Duprat
0aa2b8800c Test results verified using FileCheck rather than grep | count
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181234 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 18:45:16 +00:00
Krzysztof Parzyszek
ed6fe299cf Make references to HexagonTargetMachine "const".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181233 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 18:38:37 +00:00
Rafael Espindola
730d718b73 Remove some redundant includes in llvm-mc.cpp.
Patch by Jun Koi!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181231 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 18:19:24 +00:00
Andrew Trick
fcf79528da Rotate multi-exit loops even if the latch was simplified.
Test case by Michele Scandale!

Fixes PR10293: Load not hoisted out of loop with multiple exits.

There are few regressions with this patch, now tracked by
rdar:13817079, and a roughly equal number of improvements. The
regressions are almost certainly back luck because LoopRotate has very
little idea of whether rotation is profitable. Doing better requires a
more comprehensive solution.

This checkin is a quick fix that lacks generality (PR10293 has
a counter-example). But it trivially fixes the case in PR10293 without
interfering with other cases, and it does satify the criteria that
LoopRotate is a loop canonicalization pass that should avoid
heuristics and special cases.

I can think of two approaches that would probably be better in
the long run. Ultimately they may both make sense.

(1) LoopRotate should check that the current header would make a good
loop guard, and that the loop does not already has a sufficient
guard. The artifical SimplifiedLoopLatch check would be unnecessary,
and the design would be more general and canonical. Two difficulties:

- We need a strong guarantee that we won't endlessly rotate, so the
  analysis would need to be precise in order to avoid the
  SimplifiedLoopLatch precondition.

- Analysis like this are usually based on SCEV, which we don't want to
  rely on.

(2) Rotate on-demand in late loop passes. This could even be done by
shoving the loop back on the queue after the optimization that needs
it. This could work well when we find LICM opportunities in
multi-branch loops. This requires some work, and it doesn't really
solve the problem of SCEV wanting a loop guard before the analysis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:58:18 +00:00
Tom Stellard
32c76107d0 R600: Remove dead code from the CodeEmitter v2
v2:
  - Replace switch statement with TSFlags query

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:57 +00:00
Tom Stellard
f07b5373d7 R600: Emit config values in register / value pairs
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:51 +00:00
Eric Christopher
30cb836a20 Remove unnecessary instance variable and rework logic accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:50 +00:00
Eric Christopher
3bf2bcd96c Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:46 +00:00
Tom Stellard
4f3d8a6440 R600: Stop emitting the instruction type byte before each instruction
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181225 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:44 +00:00
Eric Christopher
93f3fed999 Don't emit .dwo sections unless they exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:42 +00:00
Tom Stellard
58bf662c06 R600: Emit ISA for CALL_FS_* instructions
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:26 +00:00
Ulrich Weigand
e5c8c24ed5 [SystemZ] Update non-pic DWARF encodings
As pointed out by Rafael Espindola, we should match the DWARF encodings
produced by GCC in both pic and non-pic modes.  This was not the case
for the non-pic case.

This patch changes all DWARF encodings to DW_EH_PE_absptr for the
non-pic case, just like GCC does.  The test case is updated to check
for both variants.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:28:30 +00:00
Adhemerval Zanella
f51d7e76ae PowerPC: Fix unimplemented relocation on ppc64
This patch handles the R_PPC64_REL64 relocation type for powerpc64
for mcjit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:21:23 +00:00
Jean-Luc Duprat
81fa2abc85 Fix add4.ll test cmdline so that it passes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181219 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:18:47 +00:00
Jean-Luc Duprat
c5cf6e5365 Provide InstCombines for the following 3 cases:
A * (1 - (uitofp i1 C)) -> select C, 0, A
B * (uitofp i1 C) -> select C, B, 0
select C, 0, A + select C, B, 0 -> select C, B, A

These come up in code that has been hand-optimized from a select to a linear blend, 
on platforms where that may have mattered. We want to undo such changes 
with the following transform:
A*(1 - uitofp i1 C) + B*(uitofp i1 C) -> select C, A, B



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181216 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 16:55:50 +00:00
Tim Northover
4c8850cd1c AArch64: use MCJIT by default and enable related tests.
This just enables some testing I'd missed after implementing MCJIT
support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 16:51:08 +00:00
Ulrich Weigand
9887cbed05 [SystemZ] Add to --enable-targets=all
This patch finally enables the SystemZ target in the default build
(with --enable-targets=all).

Patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181209 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 16:23:07 +00:00
Ulrich Weigand
735ab83b3c [SystemZ] Add configure bits
This patch wires up the SystemZ target in configure, so that it can now be
built using --enable-targets=systemz.   It is not yet included in the default
build (--enable-targets=all); this will be done by a follow-up patch.

Patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181208 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 16:22:34 +00:00
Ulrich Weigand
7207285e65 [SystemZ] Set up JIT/MCJIT test cases
This patch adds the necessary configuration bits and #ifdef's to set up
the JIT/MCJIT test cases for SystemZ.  Like other recent targets, we do
fully support MCJIT, but do not support the old JIT at all.  Set up the
lit config files accordingly, and disable old-JIT unit tests.

Patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181207 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 16:21:50 +00:00
Ulrich Weigand
097b88fff6 [SystemZ] Add MC test cases
This adds all MC tests for the SystemZ target.

Patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181206 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 16:20:58 +00:00
Ulrich Weigand
25cf4ebd50 [SystemZ] Add DebugInfo test cases
This adds all DebugInfo tests for the SystemZ target.

This version of the patch incorporates feedback from reviews by
Eric Christopher and Rafael Espindola.  Thanks to all reviewers!

Patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181205 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 16:18:29 +00:00
Ulrich Weigand
b503b49b51 [SystemZ] Add CodeGen test cases
This adds all CodeGen tests for the SystemZ target.

This version of the patch incorporates feedback from a review by
Sean Silva.  Thanks to all reviewers!

Patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181204 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 16:17:29 +00:00
Ulrich Weigand
1d09d56fe1 [SystemZ] Add back end
This adds the actual lib/Target/SystemZ target files necessary to
implement the SystemZ target.  Note that at this point, the target
cannot yet be built since the configure bits are missing.  Those
will be provided shortly by a follow-on patch.

This version of the patch incorporates feedback from reviews by
Chris Lattner and Anton Korobeynikov.  Thanks to all reviewers!

Patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181203 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 16:15:19 +00:00