Commit Graph

821 Commits

Author SHA1 Message Date
Evan Cheng
fb4db316d8 Fix a memcpy lowering bug. Even though the memcpy alignment is smaller than the desired alignment, the frame destination alignment may still be larger than the desired alignment. Don't change its alignment to something smaller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51970 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-04 23:37:54 +00:00
Dan Gohman
37cdad3e59 Fix the position of MemOperands in nodes that use variadic_ops
in DAGISelEmitter output. This bug was recently uncovered by the
addition of patterns for CALL32m and CALL64m, which are nodes
that now have both MemOperands and variadic_ops.

This bug was especially visible with PIC in various configurations,
because the new patterns are matching the indirect call code used
in many PIC configurations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51877 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-02 17:40:38 +00:00
Dan Gohman
b4106170dd Add patterns for CALL32m and CALL64m. They aren't matched in most
cases due to an isel deficiency already noted in
lib/Target/X86/README.txt, but they can be matched in this fold-call.ll
testcase, for example.

This is interesting mainly because it exposes a tricky tblgen bug;
tblgen was incorrectly computing the starting index for variable_ops
in the case of a complex pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51706 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 21:50:34 +00:00
Dan Gohman
21323f3a82 Expand small memmovs using inline code. Set the X86 threshold for expanding
memmove to a more plausible value, now that it's actually being used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51696 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 19:42:22 +00:00
Evan Cheng
f26ffe987c Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51667 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 08:22:04 +00:00
Evan Cheng
e65b9a48e3 Add nounwind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51665 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 07:09:24 +00:00
Evan Cheng
d77d4f98fb Fix PR2289: vr defined by multiple implicit_def as result of coalescing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51648 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 17:40:10 +00:00
Evan Cheng
33d3d4ad40 Teach local register allocator to deal with landing pad MBB's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51647 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 17:22:32 +00:00
Dan Gohman
caa98d3ab9 Specify a target so that this tests tests what it's intended to test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51600 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-27 17:55:57 +00:00
Dan Gohman
95628cd44a Make this test independent of the target-triple; the stack alignment
is specifically what this test depends on.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51599 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-27 17:44:23 +00:00
Nick Lewycky
3978927dfa The Linux ABI emits an extra "movl %esp, %ebp" in function prologue and
sometimes a "mov %ebp, %esp" in the epilogue.

Force these tests that rely on counting 'mov' to use i686-apple-darwin8.8.0
where they were written.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51568 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-26 20:18:56 +00:00
Evan Cheng
ef1ba3844d New loadl_pd and loadh_pd tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51525 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24 00:10:02 +00:00
Evan Cheng
cd0baf21a1 Use movlps / movhps to modify low / high half of 16-byet memory location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51501 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 21:23:16 +00:00
Dan Gohman
0b924dcef8 Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And add
load-folding table entries for PMULDQ and PMULLD.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51489 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 17:49:40 +00:00
Evan Cheng
b1938263c7 Bug: rcpps can only folds a load if the address is 16-byte aligned. Fixed many 'ps' load folding patterns in X86InstrSSE.td which are missing the proper alignment checks.
Also fixed some 80 col. violations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51462 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23 00:37:07 +00:00
Evan Cheng
d86323efc9 Add a couple of test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51441 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-22 21:19:19 +00:00
Evan Cheng
c36c0ab44b Add missing patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51435 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-22 18:56:56 +00:00
Chris Lattner
9c287c2ab4 testcase for PR2267
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51408 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-22 04:45:22 +00:00
Evan Cheng
f4ea510371 Fix PR2343. An *interesting* coalescer bug.
BB1:                                                                                                                                                  
  vr1025 = copy vr1024                                                                                                                                
  ..                                                                                                                                                  
BB2:                                                                                                                                                  
  vr1024 = op                                                                                                                                         
         = op vr1025                                                                                                                                     
  <loop eventually branch back to BB1>

Even though vr1025 is copied from vr1024, it's not safe to coalesced them since live range of vr1025 intersects the def of vr1024. This happens when vr1025 is assigned the value of the previous iteration of vr1024 in the loop.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51394 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-21 22:34:12 +00:00
Gabor Greif
f6cadc440c sabre brings to my attention that the 'tr' suffix is also obsolete
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51349 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-20 21:00:03 +00:00
Gabor Greif
722243bd40 Rename the last test with .llx extension to .ll, resolve duplicate test by renaming to isnan2. Now that no test has llx ending there is no need to search for them from dg.exp too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51328 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-20 19:52:04 +00:00
Dan Gohman
ad2ef21c76 Run vortex-bug as x86-64, which is what the original bug was triggered on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51289 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-20 00:54:39 +00:00
Dale Johannesen
e44b1bd3dc Use common where we mean common, not weak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51173 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-16 00:52:30 +00:00
Dan Gohman
f20d70d57e Fix a bug in LoopStrengthReduce that caused it to emit IR with
use-before-def. The problem comes up in code with multiple PHIs where
one PHI is being rewritten in terms of the other, but the other needs
to be casted first. LLVM rules requre the cast instruction to be
inserted after any PHI instructions, but when instructions were
inserted to replace the second PHI value with a function of the first,
they were ended up going before the cast instruction. Avoid this
problem by remembering the location of the cast instruction, when one
is needed, and inserting the expansion of the new value after it.

This fixes a bug that surfaced in 255.vortex on x86-64 when
instcombine was removed from the middle of the loop optimization
passes. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51169 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-15 23:26:57 +00:00
Dan Gohman
d64a78c9ed When bit-twiddling CondCode values for integer comparisons produces
SETOEQ, is it does with (SETEQ & SETULE), map it to SETEQ.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51112 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 18:17:09 +00:00
Evan Cheng
77f0b7a50a Instead of a vector load, shuffle and then extract an element. Load the element from address with an offset.
pshufd $1, (%rdi), %xmm0
        movd %xmm0, %eax
=>
        movl 4(%rdi), %eax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51026 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13 08:35:03 +00:00
Evan Cheng
fa7fd33a26 On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51019 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13 00:54:02 +00:00
Evan Cheng
9bfa03c6fd Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51008 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 23:04:07 +00:00
Dale Johannesen
38eb9f9ae6 New test for tail merging
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51007 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 22:59:44 +00:00
Evan Cheng
50d9e7289b When transforming a vector_shuffle to a load, the base address must not be an undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50940 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-10 06:46:49 +00:00
Evan Cheng
c81d50e0f7 Add nounwind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50931 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-10 02:22:25 +00:00
Evan Cheng
b3e0a6d75c If all sources of a PHI node are defined by an implicit_def, just emit an implicit_def instead of a copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50927 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-10 00:17:50 +00:00
Evan Cheng
23573e5be6 Add a pattern to do move the low element of a v4f32 and zero extend the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50922 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-09 23:37:55 +00:00
Evan Cheng
d880b97257 Handle a few more cases of folding load i64 into xmm and zero top bits.
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50918 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-09 21:53:03 +00:00
Evan Cheng
6c17c6bafa Simplify test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50911 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-09 19:56:32 +00:00
Evan Cheng
fd17f42bab Use movq to move low half of XMM register and zero-extend the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50874 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-08 22:35:02 +00:00
Evan Cheng
7e2ff77ef0 Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-08 00:57:18 +00:00
Evan Cheng
687bcb2be0 Add nounwind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50837 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-07 22:59:08 +00:00
Evan Cheng
7ebc06bfd8 Yet another nasty spiller bug.
%ecx = op
store %cl<kill>, (addr)
(addr) = op %al

It's not safe to unfold the last operand and eliminate store even though %cl is marked kill. It's a sub-register use which means one of its super-register(s) may be used below.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50794 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-07 00:49:28 +00:00
Anton Korobeynikov
70e616fa0b Use target triple in tests, not 'realign-stack=0' option. Per request.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50778 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06 23:09:29 +00:00
Evan Cheng
21037da713 Fix PR2287. Darwin passes mmx values in register in 64-mode, not Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50716 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06 07:23:50 +00:00
Mon P Wang
63307c335a Added addition atomic instrinsics and, or, xor, min, and max.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 19:05:59 +00:00
Chris Lattner
b61bfdb56e no need for eh info
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50658 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 18:24:33 +00:00
Dan Gohman
a779a9899a Add AsmPrinter support for emitting a directive to declare that
the code being generated does not require an executable stack.

Also, add target-specific code to make use of this on Linux
on x86. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50634 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 00:28:39 +00:00
Evan Cheng
5759f97f50 Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50619 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-04 09:15:50 +00:00
Evan Cheng
22b942aa4d Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
Chris Lattner
0b11cbacce specify an arch for non-x86 hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50576 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-02 15:11:58 +00:00
Chris Lattner
6bf30ab347 don't randomly miscompile seto/setuo just because we are in
ffastmath mode.  This fixes rdar://5902801, a miscompilation
of gcc.dg/builtins-8.c.

Bill, please pull this into Tak.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50523 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-01 07:26:11 +00:00
Arnold Schwaighofer
d2ef523673 Really commit the test checking the argument lowering behaviour on x86-64 :).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50478 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-30 09:19:47 +00:00
Chris Lattner
3fb2968f2f make the vector conversion magic handle multiple results.
We now compile test2/test3 to:

_test2:
	## InlineAsm Start
	set %xmm0, %xmm1
	## InlineAsm End
	addps	%xmm1, %xmm0
	ret
_test3:
	## InlineAsm Start
	set %xmm0, %xmm1
	## InlineAsm End
	paddd	%xmm1, %xmm0
	ret

as expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50389 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29 04:48:56 +00:00