Commit Graph

114818 Commits

Author SHA1 Message Date
Philip Reames
fb4ffccacb If a conditional branch jumps to the same target, remove the condition
Given that large parts of inst combine is restricted to instructions which have one use, getting rid of a use on the condition can help the effectiveness of the optimizer. Also, it allows the condition to potentially be deleted by instcombine rather than waiting for another pass.

I noticed this completely by accident in another test case. It's not anything that actually came from a real workload.

p.s. We should probably do the same thing for switch instructions.

Differential Revision: http://reviews.llvm.org/D8220



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231881 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 22:52:37 +00:00
Paul Robinson
107918efa2 Emit correct linkage-name attribute based on DWARF version.
There are still 4 tests that check for DW_AT_MIPS_linkage_name,
because they specify DWARF 2 or 3 in the module metadata. So, I didn't
create an explicit version-based test for the attribute.

Differential Revision: http://reviews.llvm.org/D8227


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231880 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 22:44:45 +00:00
Philip Reames
7c7b72a066 Infer known bits from dominating conditions
This patch adds limited support in ValueTracking for inferring known bits of a value from conditional expressions which must be true to reach the instruction we're trying to optimize. At this time, the feature is off by default. Once landed, I'm hoping for feedback from others on both profitability and compile time impact.

Forms of conditional value propagation have been tried in LLVM before and have failed due to compile time problems.  In an attempt to side step that, this patch only considers conditions where the edge leaving the branch dominates the context instruction. It does not attempt full dataflow.  Even with that restriction, it handles many interesting cases:
 * Early exits from functions
 * Early exits from loops (for context instructions in the loop and after the check)
 * Conditions which control entry into loops, including multi-version loops (such as those produced during vectorization, IRCE, loop unswitch, etc..)

Possible applications include optimizing using information provided by constructs such as: preconditions, assumptions, null checks, & range checks.

This patch implements two approaches to the problem that need further benchmarking.  Approach 1 is to directly walk the dominator tree looking for interesting conditions.  Approach 2 is to inspect other uses of the value being queried for interesting comparisons.  From initial benchmarking, it appears that Approach 2 is faster than Approach 1, but this needs to be further validated.  

Differential Revision: http://reviews.llvm.org/D7708



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231879 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 22:43:20 +00:00
Eric Christopher
57849e3bb4 Remove the use of the subtarget in MCCodeEmitter creation and
update all ports accordingly. Required a couple of small rewrites
in handling subtarget features during creation in PPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231861 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 22:03:14 +00:00
Rafael Espindola
f3d745cdc9 Create symbols marking the start of a section earlier.
This lets us pass the symbol to the constructor and avoid the mutable field.

This also opens the way for outputting the symbol only when needed, instead
of outputting them at the start of the file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231859 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 22:00:25 +00:00
Eric Christopher
a1cc020e29 Remove createAMDGPUMCCodeEmitter and instead just register the correct
MCCodeEmitter creation routine based on TargetMachine since the only
64-bit R600 gpus are part of the GCN target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231856 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 21:57:34 +00:00
Quentin Colombet
7775242da3 [CodeGenPrepare] Refine the cost model provided by the promotion helper.
- Use TargetLowering to check for the actual cost of each extension.
- Provide a factorized method to check for the cost of an extension:
  TargetLowering::isExtFree.
- Provide a virtual method TargetLowering::isExtFreeImpl for targets to be able
  to tune the cost of non-free extensions.

This refactoring offers a better granularity to model what really happens on
different targets.

No performance changes and very few code differences.

Part of <rdar://problem/19267165> 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231855 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 21:48:15 +00:00
Adam Nemet
31f1cc5790 [LoopAccesses] Add debug message to indicate the result of the analysis
The debug message was pretty confusing here.  It only reported the
situation with memchecks without the result of the dependence analysis.

Now it prints whether the loop is safe from the POV of the dependence
analysis and if yes, whether we need memchecks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231854 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 21:47:39 +00:00
Rafael Espindola
b3d108b39a Move a non-trivial virtual function out of line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231853 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 21:35:16 +00:00
Colin LeMahieu
7a46f6f381 [Hexagon] Adding frame index + add load/store patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231850 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 21:24:13 +00:00
Rafael Espindola
5c4720d556 clang-format code that is about to change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231848 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 21:16:18 +00:00
Colin LeMahieu
287bb3bc2b [Hexagon] Simplifying deallocret definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231847 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 21:12:32 +00:00
Rafael Espindola
931b52d665 clang-format these declarations. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231846 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 21:05:09 +00:00
Rafael Espindola
9b31a86ed9 Don't repeat names in comments. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231845 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 21:01:50 +00:00
Colin LeMahieu
25ab8bad1c [Hexagon] Separating InstHexagon from OpcodeHexagon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231844 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 20:56:22 +00:00
Nemanja Ivanovic
dc12298109 Add support for part-word atomics for PPC
http://reviews.llvm.org/D8090#inline-67337


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231843 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 20:51:07 +00:00
Chris Bieneman
b8bf97b7e1 Add new LLVM_OPTIMIZED_TABLEGEN build setting which configures, builds and uses a release tablegen build when LLVM is configured with assertions enabled.
Summary: This change leverages the cross-compiling functionality in the build system to build a release tablegen executable for use during the build.

Reviewers: resistor, rnk

Reviewed By: rnk

Subscribers: rnk, joker.eph, llvm-commits

Differential Revision: http://reviews.llvm.org/D7349

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231842 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 20:48:02 +00:00
Ahmed Bougacha
4a3cd42601 [AArch64] Avoid going through GPRs for across-vector instructions.
This adds new node types for each intrinsic.
For instance, for addv, we have AArch64ISD::UADDV, such that:
  (v4i32 (uaddv ...))
is the same as
  (v4i32 (scalar_to_vector (i32 (int_aarch64_neon_uaddv ...))))
that is,
  (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
           (i32 (int_aarch64_neon_uaddv ...)), ssub)

In a combine, we transform all such across-vector-lanes intrinsics to:

  (i32 (extract_vector_elt (uaddv ...), 0))

This has one big advantage: by making the extract_element explicit, we
enable the existing patterns for lane-aware instructions to fire.
This lets us avoid needlessly going through the GPRs.  Consider:

    uint32x4_t test_mul(uint32x4_t a, uint32x4_t b) {
        return vmulq_n_u32(a, vaddvq_u32(b));
    }

We now generate:
    addv.4s  s1, v1
    mul.4s   v0, v0, v1[0]
instead of the previous:
    addv.4s  s1, v1
    fmov     w8, s1
    dup.4s   v1, w8
    mul.4s   v0, v1, v0

rdar://20044838


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231840 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 20:45:38 +00:00
Ahmed Bougacha
4cd59eb629 [AArch64] Remove integer INSvi*lane patterns. NFCI.
Most are redundant, and they never seem to fire.

The V128 integer patterns already exist in the INS multiclass.
The duplicates only fire when the vector index type isn't i64,
because they accept "imm" instead of an explicit "i64", as the
instruction definition patterns do.

TLI::getVectorIdxTy is i64 on AArch64, so this should never happen.
Also, one of them had a typo: for i64, INSvi32lane was used.
I noticed because I mistakenly used an explicit i32 as the idx type,
and got ins.s for an i64 vector_insert.

The V64 patterns also don't seem to ever fire, as V64 vector
extract/insert are legalized to V128.

The equivalent float patterns are unique and useful, so keep them.

No functional change intended;  none exhibited on the LIT and LNT tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231838 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 20:37:19 +00:00
Chad Rosier
09fc12a14e Don't evaluate rend() on every iteration of the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231837 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 20:29:59 +00:00
David Majnemer
3e616ba7b9 LoopAccessAnalysis: Silence -Wreturn-type diagnostic from GCC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231836 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 20:23:29 +00:00
Benjamin Kramer
fede77ae26 Don't use LLVM_LIBRARY_VISIBILITY in cpp files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231831 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 20:07:44 +00:00
Bruno Cardoso Lopes
84e6358ea0 [AsmPrinter][TLOF] Reintroduce AArch64 test
Follow up from r231505.

Fix the non-determinism by using a MapVector and reintroduce the AArch64
testcase. Defer deleting the got candidates up to the end and remove
them in a bulk, avoiding linear time removal of each element.

Thanks to Renato Golin for trying it out on other platforms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231830 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 20:05:23 +00:00
Colin LeMahieu
7761008c2a [Hexagon] Adding nodes for PIC support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231829 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 20:04:44 +00:00
Colin LeMahieu
f41bfa16eb [Hexagon] Adding DuplexInst instruction format and duplex class defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231828 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 19:53:14 +00:00
Kit Barton
1f9ea3a230 Change the generation of the vmuluwm instruction to be based on the MUL opcode.
Phabricator review: http://reviews.llvm.org/D8185


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231827 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 19:49:38 +00:00
Sanjay Patel
a99cd39362 remove function names from comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231826 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 19:42:57 +00:00
Colin LeMahieu
c183848463 [Hexagon] Adding nodes for vector insert/extract lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231825 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 19:40:03 +00:00
Colin LeMahieu
b2a2499a9e [Hexagon] Renaming HexagonJT to JT and adding CP for constantpool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231824 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 19:29:53 +00:00
Adrian Prantl
e753b17efe Change the datatype of DwarfExpression::Emit(Un)Signed to (u)int64_t
so it matches the one used by ByteStreamer::Emit(U|S)LEB128.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231823 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 19:23:37 +00:00
Benjamin Kramer
f0d37a472f NVPTX: move NVPTXAllocaHoisting into the cpp file
Also initialize without using static initialization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231822 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 19:20:52 +00:00
Adam Nemet
73dff35fac [LAA-memchecks] Comment improvement
I forgot to roll this into r231816.  It was requested by Hal in D8122.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231821 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 19:12:41 +00:00
Michael Zolotukhin
7212f8bb52 Enable loop-rotate before loop-vectorize by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231820 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 19:07:41 +00:00
Adam Nemet
86dbc2b6d3 [LAA-memchecks 3/3] Introduce pointer partitions for memchecks
This is the final patch that actually introduces the new parameter of
partition mapping to RuntimePointerCheck::needsChecking.

Another API (LAI::getInstructionsForAccess) is also exposed that helps
to map pointers to instructions because ultimately we partition
instructions.

The WIP version of the Loop Distribution pass in D6930 has been adapted
to use all this.  See for example, how
InstrPartitionContainer::computePartitionSetForPointers sets up the
partitions using the above API and then calls to LAI::addRuntimeCheck
with the pointer partitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231818 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 18:54:26 +00:00
Adam Nemet
c320ed14d2 [LAA-memchecks 2/3] Move number of memcheck threshold checking to LV
Now the analysis won't "fail" if the memchecks exceed the threshold.  It
is the transform pass' responsibility to perform the check.

This allows the transform pass to further analyze/eliminate the
memchecks.  E.g. in Loop distribution we only need to check pointers
that end up in different partitions.

Note that there is a slight change of functionality here.  The logic in
analyzeLoop is that if dependence checking fails due to non-constant
distance between the pointers, another attempt is made to prove safety
of the dependences purely using run-time checks.

Before this patch we could fail the loop due to exceeding the memcheck
threshold after the first step, now we only check the threshold in the
client after the full analysis.  There is no measurable compile-time
effect but I wanted to record this here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231817 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 18:54:23 +00:00
Adam Nemet
17c9aca856 [LAA-memchecks 1/3] Split out NumComparisons checks. NFC
The check for the number of memchecks will be moved to the client of
this analysis.  Besides allowing for transform-specific thresholds, this
also lets Loop Distribution post-process the memchecks; Loop
Distribution only needs memchecks between pointers of different
partitions.

The motivation for this first patch is to untangle the CanDoRT check
from the NumComparison check before moving the NumComparison part.
CanDoRT means that we couldn't determine the bounds for the pointer.
Note that NumComparison is set independent of this flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231816 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 18:54:19 +00:00
Sanjay Patel
9677d4f3f3 remove names from comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231813 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 18:41:22 +00:00
Sanjay Patel
3885990176 fix typos; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231812 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 18:37:05 +00:00
Benjamin Kramer
5b536e4af0 NVPTX: Remove copy of LLVMInitializeNVPTXAsmPrinter.
If anyone is using this for some strange reason,
LLVMInitializeNVPTXAsmPrinter does exactly the same thing and is what
other LLVM tools are calling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231810 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 18:19:24 +00:00
Benjamin Kramer
7b3db42f63 Hexagon: Remove unused InstrMapping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231809 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 18:19:16 +00:00
Adam Nemet
8e7d56f6f7 [LoopAccesses 3/3] Print the dependences with -analyze
The dependences are now expose through the new getInterestingDependences
API so we can use that with -analyze too and fix the FIXME.

This lets us remove the test that relied on -debug to check the
dependences.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231807 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 17:40:43 +00:00
Adam Nemet
7063c7e084 [LoopAccesses 2/3] Allow querying of interesting dependences
Gather an array of interesting dependences rather than just failing
after the first unsafe one and regarding the loop unsafe.  Loop
Distribution needs to be able to collect all dependences in order to
isolate the dependence cycles into their own partition.

Since the dependence checking algorithm is quadratic in terms of
accesses sharing the same underlying pointer, I am applying a cut-off
threshold (MaxInterestingDependence).  Exceeding that, the logic reverts
back to the original approach deeming the loop unsafe upon encountering
the first unsafe dependence.

The main idea of the patch is to split isDepedent from directly
answering the question whether the dep is safe for vectorization to
return a dependence type which then gets mapped to old boolean result
using Dependence::isSafeForVectorization.

Tested that this was compile-time neutral on SpecINT2006 LTO bitcode
inputs.  No assembly change on the testsuite including external.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231806 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 17:40:37 +00:00
Adam Nemet
0ddb48c2f8 [LoopAccesses 1/3] Expose MemoryDepChecker to LAA users
LoopDistribution needs to query various results of the dependence
analysis.  This series will expose some more APIs and state of the
dependence checker.

This patch is a simple one to just expose the DepChecker instance.  The
set is compile-time neutral measured with LTO bitcode files of
SpecINT2006.  Also there is no assembly change on the testsuite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231805 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 17:40:34 +00:00
Rafael Espindola
0f4df6dc6f Store an optional section start label in MCSection.
This makes code that uses section relative expressions (debug info) simpler and
less brittle.

This is still a bit awkward as the symbol is created late and has to be
stored in a mutable field.

I will move the symbol creation earlier in the next patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231802 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 16:58:10 +00:00
Sanjay Patel
f681b3f13f remove function names from comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231801 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 16:42:24 +00:00
Igor Laevsky
68beb2a9ec Teach lowering to correctly handle invoke statepoint and gc results tied to them. Note that we still can not lower gc.relocates for invoke statepoints.
Also it extracts getCopyFromRegs helper function in SelectionDAGBuilder as we need to be able to customize type of the register exported from basic block during lowering of the gc.result.
(Resubmitting this change after not being able to reproduce buildbot failure)

Differential Revision: http://reviews.llvm.org/D7760



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231800 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 16:26:48 +00:00
Chad Rosier
e891f49ad5 [BranchFolding] Remove MMOs during tail merge to preserve dependencies.
When tail merging it may be necessary to remove MMOs from memory operations to
ensures later passes (e.g., MI sched) conservatively compute dependencies.
Currently, we only remove the MMO from the common tail if the MMO doesn't match
with the relative instruction in the non-common tail(s).

A more robust solution would be to add multiple MMOs from the duplicate MIs to
the new MI. Currently ScheduleDAGInstrs.cpp ignores all MMOs on instructions
with multiple MMOs, so this solution is equivalent for the time being.

No test case included as this is incredibly difficult to reproduce.

Patch was a collaborative effort between Ana Pazos and myself.
Phabricator: http://reviews.llvm.org/D7769

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231799 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 16:22:52 +00:00
Tom Stellard
d472057ca2 R600/SI: Add _IDXEN and _BOTHEN variants for buffer_store
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231798 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 16:16:51 +00:00
Tom Stellard
29e7485cda R600/SI: Re-order MUBUF operands to match asm strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231797 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 16:16:49 +00:00
Tom Stellard
c2e1ba5d21 R600/SI: Move kill flag to second instruction when splitting SMRD
This fixes a machine verifier error in the salu-to-valu.ll, which
would have been exposed by a future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231796 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 16:16:48 +00:00