Commit Graph

881 Commits

Author SHA1 Message Date
Bill Wendling
aa8f8889a8 Darwin doesn't need exception handling information for the "move" info when
debug information is being output, because it's leet!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52994 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01 23:34:48 +00:00
Evan Cheng
6547e406cf Avoid creating expensive comment string if it's not going to be printed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52992 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01 23:18:29 +00:00
Dan Gohman
2dad0250f6 Prune a few dependencies on MachineFunction.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52976 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01 18:15:35 +00:00
Owen Anderson
605041e5a8 Make the subregister hashtable output more readable by wrapping the lines,
and mark it const along with the associated changes to TargetRegisterInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52966 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01 17:34:38 +00:00
Owen Anderson
57ce0319b7 Implement suggestions from Chris:
- Use a more accurate heuristic for the size of the hashtable.
  - Use bitwise and instead of modulo since the size is a power of two.
  - Use new[] instead of malloc().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52951 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01 07:02:30 +00:00
Owen Anderson
f4f9c4f1cf Replace the dynamically computed std::set lookup method for subregisters with a hashtable-based
version that is computed by tblgen at the time LLVM is compiled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52945 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01 00:18:52 +00:00
Dan Gohman
4406604047 Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01 00:05:16 +00:00
Dan Gohman
87060f55f2 Update comments to new-style syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52925 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-30 21:00:56 +00:00
Dan Gohman
9665c2ae79 Reorder the fields in TargetLowering to require less padding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52919 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-30 20:36:26 +00:00
Dan Gohman
3d3c3e0cfa Change bools to 1-bit bitfields to shrink ArgListEntry slightly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52918 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-30 20:33:57 +00:00
Dan Gohman
a44b674a42 Replace some std::vectors that showed up in heap profiling with
SmallVectors. Change the signature of TargetLowering::LowerArguments
to avoid returning a vector by value, and update the two targets
which still use this directly, Sparc and IA64, accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52917 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-30 20:31:15 +00:00
Evan Cheng
2036835346 Eliminate TargetRegisterDesc::ImmSubRegs. It's no longer in use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52892 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-30 07:32:56 +00:00
Anton Korobeynikov
28a2b54580 Start refactoring of asmprinters: provide a TAI hook, which will select a 'section kind' for a global.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52868 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-28 13:45:57 +00:00
Owen Anderson
1360b7d8f8 Cache subregister relationships in a set in TargetRegisterInfo to allow faster lookups.
This speeds up LiveVariables from 0.6279s to 0.6165s on kimwitu++.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52818 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-27 06:56:04 +00:00
Dale Johannesen
b5dae00325 Fixes the last x86-64 test failure in compat.exp:
<16 x float> is 64-byte aligned (for some reason),
which gets us into the stack realignment code.  The
computation changing FP-relative offsets to SP-relative
was broken, assiging a spill temp to a location
also used for parameter passing.  This
fixes it by rounding up the stack frame to a multiple
of the largest alignment (I concluded it wasn't fixable
without doing this, but I'm not very sure.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52750 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-26 01:51:13 +00:00
Chris Lattner
bc52cada09 Switch the PPC backend and target-independent JIT to use the libsystem
InvalidateInstructionCache method instead of calling through
a hook on the JIT.  This is a host feature, not a target feature.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52734 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-25 17:18:44 +00:00
Anton Korobeynikov
210539ebc4 Provide generic hooks for icache invalidation. Add PPC implementation.
Patch by Gary Benson!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52418 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-17 17:30:05 +00:00
Evan Cheng
58dcb0e0cd Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 07:33:11 +00:00
Duncan Sands
d4b9c17fb7 Disable some DAG combiner optimizations that may be
wrong for volatile loads and stores.  In fact this
is almost all of them!  There are three types of
problems: (1) it is wrong to change the width of
a volatile memory access.  These may be used to
do memory mapped i/o, in which case a load can have
an effect even if the result is not used.  Consider
loading an i32 but only using the lower 8 bits.  It
is wrong to change this into a load of an i8, because
you are no longer tickling the other three bytes.  It
is also unwise to make a load/store wider.  For
example, changing an i16 load into an i32 load is
wrong no matter how aligned things are, since the
fact of loading an additional 2 bytes can have
i/o side-effects.  (2) it is wrong to change the
number of volatile load/stores: they may be counted
by the hardware.  (3) it is wrong to change a volatile
load/store that requires one memory access into one
that requires several.  For example on x86-32, you
can store a double in one processor operation, but to
store an i64 requires two (two i32 stores).  In a
multi-threaded program you may want to bitcast an i64
to a double and store as a double because that will
occur atomically, and be indivisible to other threads.
So it would be wrong to convert the store-of-double
into a store of an i64, because this will become two
i32 stores - no longer atomic.  My policy here is
to say that the number of processor operations for
an illegal operation is undefined.  So it is alright
to change a store of an i64 (requires at least two
stores; but could be validly lowered to memcpy for
example) into a store of double (one processor op).
In short, if the new store is legal and has the same
size then I say that the transform is ok.  It would
also be possible to say that transforms are always
ok if before they were illegal, whether after they
are illegal or not, but that's more awkward to do
and I doubt it buys us anything much.
However this exposed an interesting thing - on x86-32
a store of i64 is considered legal!  That is because
operations are marked legal by default, regardless of
whether the type is legal or not.  In some ways this
is clever: before type legalization this means that
operations on illegal types are considered legal;
after type legalization there are no illegal types
so now operations are only legal if they really are.
But I consider this to be too cunning for mere mortals.
Better to do things explicitly by testing AfterLegalize.
So I have changed things so that operations with illegal
types are considered illegal - indeed they can never
map to a machine operation.  However this means that
the DAG combiner is more conservative because before
it was "accidentally" performing transforms where the
type was illegal because the operation was nonetheless
marked legal.  So in a few such places I added a check
on AfterLegalize, which I suppose was actually just
forgotten before.  This causes the DAG combiner to do
slightly more than it used to, which resulted in the X86
backend blowing up because it got a slightly surprising
node it wasn't expecting, so I tweaked it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52254 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-13 19:07:40 +00:00
Duncan Sands
4c54067f67 If queried as to whether an operation is legal
for a particular MVT, return false if the type
is illegal rather than barfing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52229 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-12 09:01:30 +00:00
Duncan Sands
8e4eb09b1e Remove comparison methods for MVT. The main cause
of apint codegen failure is the DAG combiner doing
the wrong thing because it was comparing MVT's using
< rather than comparing the number of bits.  Removing
the < method makes this mistake impossible to commit.
Instead, add helper methods for comparing bits and use
them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52098 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-08 20:54:56 +00:00
Duncan Sands
83ec4b6711 Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-06 12:08:01 +00:00
Dale Johannesen
bd44c2e383 Expand documentation of StringConstantPrefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51911 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-03 18:15:03 +00:00
Dale Johannesen
428ac54894 Add StringConstantPrefix to control what the
assembler names of string constants look like.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51909 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-03 18:09:06 +00:00
Evan Cheng
652f7ea955 Revert 51775.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51795 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-30 22:47:19 +00:00
Evan Cheng
babf11f249 Patches for building llvm on Solaris x86. Contributed by Nathan Keynes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51775 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-30 17:16:20 +00:00
Dan Gohman
1baa88e3de Prune and tidy #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51697 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 19:52:31 +00:00
Bill Wendling
8370d38ade Add a flag to indicate that an instruction is as cheap (or cheaper) than a move
instruction to execute. This can be used for transformations (like two-address
conversion) to remat an instruction instead of generating a "move"
instruction. The idea is to decrease the live ranges and register pressure and
all that jazz.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51660 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28 22:54:52 +00:00
Bill Wendling
13d57320bd Remove warnings about unused parameters and shadowed variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51266 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-19 20:15:12 +00:00
Evan Cheng
0ef8de30fa Fix typos and comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51165 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-15 22:13:02 +00:00
Evan Cheng
f0df03134e Make use of vector load and store operations to implement memcpy, memmove, and memset. Currently only X86 target is taking advantage of these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51140 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-15 08:39:06 +00:00
Evan Cheng
9bfa03c6fd Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51008 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 23:04:07 +00:00
Bill Wendling
9f8fea3531 Constify the machine instruction passed into the
"is{Trivially,Really}ReMaterializable" methods.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51001 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 20:54:26 +00:00
Evan Cheng
f86f211ec2 Forgot this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50993 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 20:08:05 +00:00
Evan Cheng
c6c6a3e2b3 Make OpActionsCapacity multiple of 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50917 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-09 21:50:23 +00:00
Duncan Sands
671fa97a4b Output correct exception handling and frame info
on x86-64 linux.  This causes no regressions on
32 bit linux and 32 bit ppc.  More tests pass
on 64 bit ppc with no regressions.  I didn't
turn on eh on 64 bit linux because the intrinsics
needed to compile the eh runtime aren't done
yet.  But if you turn it on and link with the
mainline runtime then eh seems to work fine
on x86-64 linux with this patch.  Thanks to
Dale for testing.  The main point of the patch
is that if you output that some object is
encoded using 4 bytes you had better not output
8 bytes for it: the patch makes everything
consistent.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50825 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-07 19:11:09 +00:00
Mon P Wang
63307c335a Added addition atomic instrinsics and, or, xor, min, and max.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 19:05:59 +00:00
Evan Cheng
34cd4a484e Fix more -Wshorten-64-to-32 warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50659 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 18:30:58 +00:00
Dan Gohman
a779a9899a Add AsmPrinter support for emitting a directive to declare that
the code being generated does not require an executable stack.

Also, add target-specific code to make use of this on Linux
on x86. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50634 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 00:28:39 +00:00
Arnold Schwaighofer
30e62c098b Tail call optimization improvements:
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.

Initial PowerPC tail call implementation:

Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).  
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if 
  caller and callee are fastcc
  call is a tail call (in tail call position, call followed by ret)
  no variable argument lists or byval arguments
  option -tailcallopt is enabled
Supported:
 * non pic tail calls on linux/darwin
 * module-local tail calls on linux(PIC/GOT)/darwin(PIC)
 * inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.

A test checking the argument lowering behaviour on x86-64 was added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-30 09:16:33 +00:00
Chris Lattner
5a09690446 Implement a signficant optimization for inline asm:
When choosing between constraints with multiple options,
like "ir", test to see if we can use the 'i' constraint and
go with that if possible.  This produces more optimal ASM in
all cases (sparing a register and an instruction to load it),
and fixes inline asm like this:

void test () {
  asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14));
}

Previously we would dump "42" into a memory location (which
is ok for the 'm' constraint) which would cause a problem
because the 'c' modifier is not valid on memory operands.

Isn't it great how inline asm turns 'missed optimization'
into 'compile failed'??

Incidentally, this was the todo in 
PowerPC/2007-04-24-InlineAsm-I-Modifier.ll

Please do NOT pull this into Tak.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50315 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-27 00:37:18 +00:00
Chris Lattner
4376fea663 Move a bunch of inline asm code out of line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50313 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-27 00:09:47 +00:00
Chris Lattner
5e764233f3 A few inline asm cleanups:
- Make targetlowering.h fit in 80 cols.
  - Make LowerAsmOperandForConstraint const.
  - Make lowerXConstraint -> LowerXConstraint
  - Make LowerXConstraint return a const char* instead of taking a string byref.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50312 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-26 23:02:14 +00:00
Anton Korobeynikov
769b481e9f Add facility for pre-RA passes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50165 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-23 18:22:28 +00:00
Anton Korobeynikov
45709ae09b Make stack alignment options global for all targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50157 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-23 18:18:10 +00:00
Nicolas Geoffray
51cc3c13ea Correlate stubs with functions in JIT: when emitting a stub, the JIT tells the memory manager which function
the stub will resolve.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49814 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-16 20:46:05 +00:00
Nicolas Geoffray
52e724ad7e Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-16 20:10:13 +00:00
Evan Cheng
8102703d70 Sort sub-registers and super-registers lists according to super-sub register relations. e.g. X86::RAX sub-register list is EAX, AX, AL, AH (order of last two are not guaranteed).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49714 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-15 07:56:03 +00:00
Dan Gohman
29e4bdbf27 Fix const-correctness issues with the SrcValue handling in the
memory intrinsic expansion code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49666 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-14 17:55:48 +00:00
Dale Johannesen
3541af73b6 Reverse sense of unwind-tables option. This means
stack tracebacks on Darwin x86-64 won't work by default;
nevertheless, everybody but me thinks this is a good idea.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-14 17:54:17 +00:00