Aaron Watry
6c4b8fe9dd
R600: Fix spelling error in comment
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our -> or
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184756 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 16:57:57 +00:00
Tom Stellard
4010e43810
R600/SI: Expand sub for v2i32 and v4i32 for SI
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Also add a v2i32 test to the existing v4i32 test.
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184482 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 21:55:37 +00:00
Tom Stellard
fe91c515d7
R600/SI: Expand add for v2i32 and v4i32
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Also add SI tests to existing file and a v2i32 test for both
R600 and SI.
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184481 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 21:55:30 +00:00
Tom Stellard
eb3aa070c9
R600: Expand v2i32 load/store instead of custom lowering
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The custom lowering causes llc to crash with a segfault.
Ideally, the custom lowering can be fixed, but this allows
programs which load/store v2i32 to work without crashing.
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184480 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 21:55:23 +00:00
Bill Wendling
ba54bca472
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 21:36:55 +00:00
Matt Arsenault
ad966ea7a8
Move StructurizeCFG out of R600 to generic Transforms.
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Register it with PassManager
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 20:18:24 +00:00
Matt Arsenault
70a3dc1bc2
Use GetUnderlyingObject instead of custom function
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184261 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 23:37:58 +00:00
Bill Wendling
b44193dde1
Remove dead prototype.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184173 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 06:24:14 +00:00
Vincent Lejeune
f7c9b95f94
R600: PV stores Reg id, not index
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184117 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-17 20:16:40 +00:00
Vincent Lejeune
98f5cf8000
R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen.
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Fixes rv7x0 bug in Heaven reported here:
https://bugs.freedesktop.org/show_bug.cgi?id=64257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184116 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-17 20:16:26 +00:00
Tom Stellard
5aee09da12
R600: Add SI load support for v[24]i32 and store for v2i32
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Also add a seperate vector lit test file, since r600 doesn't seem to handle
v2i32 load/store yet, but we can test both for SI.
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184021 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-15 00:09:31 +00:00
Tom Stellard
d6055262d2
R600: Use correct encoding for Vertex Fetch instructions on Cayman
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Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184016 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-14 22:12:30 +00:00
Tom Stellard
4efccd0fb1
R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman
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We were using RAT_INST_STORE_RAW, which seemed to work, but the docs
say this instruction doesn't exist for Cayman, so it's probably safer
to use a documented instruction instead.
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184015 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-14 22:12:24 +00:00
Tom Stellard
c30b232349
R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg class
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Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184014 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-14 22:12:19 +00:00
Tom Stellard
2def95fc1e
R600: Move instruction encoding definitions into a separate .td file
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Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184013 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-14 22:12:09 +00:00
Tom Stellard
2948e693cb
R600: Don't try to fix reg class when copying IMPLICIT_DEF to a register
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The test case for this is way too complex to be useful as a lit test,
and I was unable to reduce it.
https://bugs.freedesktop.org/show_bug.cgi?id=65438
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183937 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-13 20:14:00 +00:00
Benjamin Kramer
6c59c7a6fd
R600: Make helper functions static.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183744 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 13:32:25 +00:00
Vincent Lejeune
843c6c2d0e
R600: Use a refined heuristic to choose when switching clause
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This is using a hint from AMD APP OpenCL Programming Guide with
empirically tweaked parameters.
I used Unigine Heaven 3.0 to determine best parameters on my system
(i7 2600/Radeon 6950/Kernel 3.9.4) the benchmark :
it went from 38.8 average fps to 39.6, which is ~3% gain.
(Lightmark 2008.2 gain is much more marginal: from 537 to 539)
There is no lit test provided as the parameter were determined
empirically and it it would be nearly impossiblet to find a test
program that check for optimal behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183593 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 23:30:34 +00:00
Vincent Lejeune
b01bdf87ff
R600: Anti dep better handled in tex clause
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183592 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 23:30:26 +00:00
Tom Stellard
df74b86e1e
R600: Fix calculation of stack offset in AMDGPUFrameLowering
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We weren't computing structure size correctly and we were relying on
the original alloca instruction to compute the offset, which isn't
always reliable.
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183568 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:52:05 +00:00
Tom Stellard
3ff0abfaab
R600: Rework subtarget info and remove AMDILDevice classes
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This should simplify the subtarget definitions and make it easier to
add new ones.
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183566 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:37:48 +00:00
Bill Wendling
b5632b5b45
Don't cache the instruction and register info from the TargetMachine, because
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the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:28:55 +00:00
Tom Stellard
ce961477be
R600: Fix the fetch limits for R600 generation GPUs
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Reviewed-by: Vincent Lejeune <vljn@ovi.com>
https://bugs.freedesktop.org/show_bug.cgi?id=64257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183560 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:28:55 +00:00
Tom Stellard
630547ada4
R600: Move Subtarget feature definitions into AMDGPU.td
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This is the convention used by the other targets.
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183559 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:28:49 +00:00
Tom Stellard
6f3b49323c
R600: Remove unnecessary include
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Reviewed-by: Vincent Lejeune <vljn@ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183558 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:28:43 +00:00
Benjamin Kramer
1983a4cbf1
R600: Don't compare iterators of different maps.
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Found be libstdc's debug mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183549 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 19:59:34 +00:00
Benjamin Kramer
2e0cebd881
Vincent says the element is at most once in the vector, so we don't need a full std::remove.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183541 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 18:18:12 +00:00
Benjamin Kramer
47b0c0a9a0
R600: Fix a potential iterator invalidation issue.
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As a bonus this reduces the loop from O(n^2) to O(n).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183532 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 16:13:49 +00:00
Vincent Lejeune
74f03455e5
R600: Remove an extra break in R600OptimizeVectorRegisters.cpp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183528 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 15:44:53 +00:00
Vincent Lejeune
81c5d11c25
R600: Rewrite an awkward loop in R600MachineScheduler
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183458 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 23:08:32 +00:00
Vincent Lejeune
5f035d048e
R600: Remove leftover code in R600MachineScheduler.cpp
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Spotted by Benjamin Kramer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 14:18:29 +00:00
Bill Wendling
2ed7659b88
Cast to the correct type. Pointer, not reference.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183385 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 05:39:29 +00:00
NAKAMURA Takumi
0ac857462f
R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized]
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FIXME: Is it false alarm?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183371 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 02:15:12 +00:00
NAKAMURA Takumi
7b6d32a361
R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183370 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 02:15:06 +00:00
NAKAMURA Takumi
3ebcf388cd
Trailing linefeed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183369 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 02:15:00 +00:00
Bill Wendling
b88cef5a16
Cast to the proper type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183365 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 01:04:21 +00:00
Tom Stellard
c170230b3a
R600: Replace predicate loop with predicate function
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183351 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 23:39:50 +00:00
Vincent Lejeune
f3d6e32c09
R600: Add a pass that merge Vector Register
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Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 21:38:04 +00:00
Vincent Lejeune
512119770e
R600: Schedule copy from phys register at beginning of block
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It allows regalloc pass to remove them by trivially assigning associated reg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 20:27:35 +00:00
Tom Stellard
ad7ecc65b1
R600: Make sure to schedule AR register uses and defs in the same clause
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Reviewed-by: vljn at ovi.com
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183294 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 03:43:06 +00:00
Rafael Espindola
6afb65c2b7
Revert "R600: Add a pass that merge Vector Register"
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This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183286 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 01:48:30 +00:00
Vincent Lejeune
bbbdba891b
R600: Add a pass that merge Vector Register
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183279 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 23:17:26 +00:00
Vincent Lejeune
e67a4afb5d
R600: Const/Neg/Abs can be folded to dot4
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183278 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 23:17:15 +00:00
Vincent Lejeune
98017a015b
R600: Swizzle texture/export instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 15:04:53 +00:00
Aaron Ballman
f3d3952a8c
Silencing an MSVC warning about mixing bool and unsigned int.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 01:03:03 +00:00
Tom Stellard
e5fcc0dee4
R600/SI: Add support for work item and work group intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:40:18 +00:00
Tom Stellard
e7397ee81a
R600/SI: Add a calling convention for compute shaders
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183137 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:40:11 +00:00
Tom Stellard
e86f9d70ca
R600/SI: Custom lower i64 sign_extend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183136 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:40:03 +00:00
Tom Stellard
17e8ad67f0
R600/SI: Adjust some instructions' out register class after ISel
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This is necessary to avoid generating VGPR to SGPR copies in some
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:39:58 +00:00
Tom Stellard
b89a467559
R600/SI: Handle REG_SEQUENCE in fitsRegClass()
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183134 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:39:54 +00:00