Commit Graph

10424 Commits

Author SHA1 Message Date
Tim Northover
fe6f4e4d31 AArch64/ARM64: port more tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207101 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:11:46 +00:00
Benjamin Kramer
f43438b6c3 X86: Emit test instead of constant shift + compare if the shift result is unused.
This allows us to compile
  return (mask & 0x8 ? a : b);
into
  testb $8, %dil
  cmovnel %edx, %esi
instead of
  andl  $8, %edi
  shrl  $3, %edi
  cmovnel %edx, %esi

which we formed previously because dag combiner canonicalizes setcc of and into shift.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207088 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 08:15:31 +00:00
Saleem Abdulrasool
ac30dfdaa3 MC: move test from Generic to COFF
This is a COFF specific test, move it to COFF to fix the Hexagon buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207030 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 21:41:07 +00:00
Saleem Abdulrasool
49babc916a MC: honour IMAGE_SCN_CNT_INITIALIZED_DATA
Emit the flag to indicate to the assembler that a section contains data if there
is pre-populated data present.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207028 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 21:29:34 +00:00
Quentin Colombet
28a24ca471 [ARM64] Fix the information we give to the peephole optimizer for comparison.
ANDS does not use the same encoding scheme as other xxxS instructions (e.g.,
ADDS). Take that into account to avoid wrong peephole optimization.

<rdar://problem/16693089>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207020 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 20:43:38 +00:00
Matt Arsenault
6cd6974e56 R600: Add a test that used to be broken that I forgot to add
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207017 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 19:45:05 +00:00
Kevin Qin
81ea345894 [ARM64] Enable feature predicates for NEON / FP / CRYPTO.
AArch64 has feature predicates for NEON, FP and CRYPTO instructions.
This allows the compiler to generate code without using FP, NEON
or CRYPTO instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206949 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 06:22:48 +00:00
Reid Kleckner
aaff72bcd8 Fix test/CodeGen/arm.ll
The 'CHECK: add' line was occasionally matching against the filename,
breaking the subsequent CHECK-NOT.  Also use CHECK-LABEL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206936 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 01:09:29 +00:00
Matt Arsenault
3682fdabef R600: Emit error instead of unreachable on function call
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206904 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 16:42:00 +00:00
Elena Demikhovsky
b84cc10c3c AVX-512: store and truncstore for i1 values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206897 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 14:13:10 +00:00
Tim Northover
2872e118b3 AArch64/ARM64: more testing from AArch64 to ARM64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206889 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 12:45:47 +00:00
Tim Northover
8b36f98fd5 AArch64/ARM64: make use of ANDS and BICS instructions for comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206888 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 12:45:42 +00:00
Tim Northover
c499ecd1d1 AArch64/ARM64: add extra testing from AArch64 to ARM64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 12:45:32 +00:00
Tim Northover
ba61446a56 AArch64/ARM64: enable various AArch64 tests on ARM64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206877 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 10:10:26 +00:00
Tim Northover
0e277d18bb AArch64/ARM64: add patterns for scalar_to_vector/extract pairs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206876 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 10:10:18 +00:00
Tim Northover
85974bc77e AArch64/ARM64: mark fmul intrinsic as commutative.
This gives DAG patterns matching indexed patterns where either side is an
indexed vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206875 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 10:10:14 +00:00
Tim Northover
74bd57b16b ARM: disable emission of __XYZvfp in soft-float environment.
The point of these calls is to allow Thumb-1 code to make use of the VFP unit
to perform its operations. This is not desirable with -msoft-float, since most
of the reasons you'd want that apply equally to the runtime library.

rdar://problem/13766161

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206874 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 10:10:09 +00:00
Hao Liu
07dcdc7c90 Fix an infinite loop bug in DAG Combine about keeping transfering between ANY_EXTEND and SIGN_EXTEND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206873 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 09:57:06 +00:00
Lang Hames
53b4d83b63 [X86] Don't use BZHI for short masks (>=32 bits). Thanks to Ben Kramer for the
review.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206869 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 07:40:34 +00:00
Matt Arsenault
3ddf868b04 R600: Make sign_extend_inreg legal.
Don't know why I didn't just do this in the first place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206862 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 03:49:30 +00:00
Jiangning Liu
0240286c23 [AArch64] Enable global merge pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206861 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 03:33:26 +00:00
Quentin Colombet
8959c39450 [CodeGenPrepare] Use APInt to check the value of the immediate in a and
while checking candidate for bit field extract.
Otherwise the value may not fit in uint64_t and this will trigger an
assertion.

This fixes PR19503.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206834 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 01:20:34 +00:00
Yi Jiang
5d473a0831 ARM64: Combine shifts and uses from different basic block to bit-extract instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206774 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 19:34:27 +00:00
Duncan P. N. Exon Smith
9a11d668f9 Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"
This reverts commit r206707, reapplying r206704.  The preceding commit
to CalcSpillWeights should have sorted out the failing buildbots.

<rdar://problem/14292693>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206766 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 17:57:07 +00:00
Eli Bendersky
85af3e7445 Fix the test: DCE optimized away everything.
Use volatile store to protect the generated PTX from DCE.

Patch by Jingyue Wu.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206763 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 17:23:12 +00:00
Michael Zolotukhin
d329c79f16 Reapply r206732. This time without optimization of branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206749 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 12:01:33 +00:00
NAKAMURA Takumi
2b3433557f llvm/test/CodeGen/X86/bmi.ll: Relax expressions for targeting win32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206743 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 11:01:46 +00:00
Lang Hames
f69bb5e43c [X86] ISEL (and X, <constant mask>) to BZHI when BMI2 is available.
Generating BZHI in the variable mask case, i.e. (and X, (sub (shl 1, N), 1)),
was already supported, but we were missing the constant-mask case. This patch
fixes that.

<rdar://problem/15480077>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206738 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 08:18:53 +00:00
Chandler Carruth
81549a0a39 Revert r206732 which is causing llc to crash on most of the build bots.
Original commit message:
  Implement builtins for safe division: safe.sdiv.iN, safe.udiv.iN,
  safe.srem.iN, safe.urem.iN (iN = i8, i61, i32, or i64).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206735 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 07:11:15 +00:00
Michael Zolotukhin
7d5100d14e Implement builtins for safe division: safe.sdiv.iN, safe.udiv.iN, safe.srem.iN,
safe.urem.iN (iN = i8, i16, i32, or i64).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206732 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 05:33:09 +00:00
Duncan P. N. Exon Smith
f44eda4764 Revert "blockfreq: Rewrite BlockFrequencyInfoImpl"
This reverts commit r206704, as expected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206707 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-19 22:46:00 +00:00
Duncan P. N. Exon Smith
c404a5334e Revert "blockfreq: Temporarily turn on -debug-only=block-freq"
This reverts commit r206705, as planned.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206706 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-19 22:45:44 +00:00
Duncan P. N. Exon Smith
69552aa77e blockfreq: Temporarily turn on -debug-only=block-freq
These tests fail after my BlockFrequencyInfo rewrite on two buildbots
[1][2].  I can't reproduce it locally, so I'm temporarily turning on
-debug-only=block-freq so I can find the problem.

[1]: http://bb.pgr.jp/builders/ninja-x64-msvc-RA-centos6/builds/1860
[2]: http://llvm-amd64.freebsd.your.org/b/builders/clang-i386-freebsd/builds/18477

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206705 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-19 22:40:56 +00:00
Duncan P. N. Exon Smith
f465370a49 Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"
This reverts commit r206677, reapplying my BlockFrequencyInfo rewrite.

I've done a careful audit, added some asserts, and fixed a couple of
bugs (unfortunately, they were in unlikely code paths).  There's a small
chance that this will appease the failing bots [1][2].  (If so, great!)

If not, I have a follow-up commit ready that will temporarily add
-debug-only=block-freq to the two failing tests, allowing me to compare
the code path between what the failing bots and what my machines (and
the rest of the bots) are doing.  Once I've triggered those builds, I'll
revert both commits so the bots go green again.

[1]: http://bb.pgr.jp/builders/ninja-x64-msvc-RA-centos6/builds/1816
[2]: http://llvm-amd64.freebsd.your.org/b/builders/clang-i386-freebsd/builds/18445

<rdar://problem/14292693>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206704 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-19 22:34:26 +00:00
Yaron Keren
64b2297786 Patch by Vadim Chugunov
Win64 stack unwinder gets confused when execution flow "falls through" after
a call to 'noreturn' function. This fixes the "missing epilogue" problem by 
emitting a trap instruction for IR 'unreachable' on x86_x64-pc-windows.

A secondary use for it would be for anyone wanting to make double-sure that
'noreturn' functions, indeed, do not return.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206684 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-19 13:47:43 +00:00
Duncan P. N. Exon Smith
2033057de8 Revert "blockfreq: Rewrite BlockFrequencyInfoImpl" (#2)
This reverts commit r206666, as planned.

Still stumped on why the bots are failing.  Sanitizer bots haven't
turned anything up.  If anyone can help me debug either of the failures
(referenced in r206666) I'll owe them a beer.  (In the meantime, I'll be
auditing my patch for undefined behaviour.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206677 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-19 00:42:46 +00:00
Duncan P. N. Exon Smith
036e26bc29 Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl" (#2)
This reverts commit r206628, reapplying r206622 (and r206626).

Two tests are failing only on buildbots [1][2]: i.e., I can't reproduce
on Darwin, and Chandler can't reproduce on Linux.  Asan and valgrind
don't tell us anything, but we're hoping the msan bot will catch it.

So, I'm applying this again to get more feedback from the bots.  I'll
leave it in long enough to trigger builds in at least the sanitizer
buildbots (it was failing for reasons unrelated to my commit last time
it was in), and hopefully a few others.... and then I expect to revert a
third time.

[1]: http://bb.pgr.jp/builders/ninja-x64-msvc-RA-centos6/builds/1816
[2]: http://llvm-amd64.freebsd.your.org/b/builders/clang-i386-freebsd/builds/18445

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206666 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 22:30:03 +00:00
Chad Rosier
6c4ec69c6b [ARM64] Ports the Cortex-A53 Machine Model description from AArch64.
Summary:
This port includes the rudimentary latencies that were provided for
the Cortex-A53 Machine Model in the AArch64 backend. It also changes
the SchedAlias for COPY in the Cyclone model to an explicit
WriteRes mapping to avoid conflicts in other subtargets.

Differential Revision: http://reviews.llvm.org/D3427
Patch by Dave Estes <cestes@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206652 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 21:22:04 +00:00
Yaron Keren
904f8dcaa4 Expanded test for x86-pc-windows-gnu and x86_64-pc-windows-gnu environments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206649 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 21:10:11 +00:00
Adam Nemet
d290fa608f [X86] Improve buildFromShuffleMostly for AVX
For a 256-bit BUILD_VECTOR consisting mostly of shuffles of 256-bit vectors,
both the BUILD_VECTOR and its operands may need to be legalized in multiple
steps.  Consider:

(v8f32 (BUILD_VECTOR (extract_vector_elt (v8f32 %vreg0,) Constant<1>),
                     (extract_vector_elt %vreg0, Constant<2>),
                     (extract_vector_elt %vreg0, Constant<3>),
                     (extract_vector_elt %vreg0, Constant<4>),
                     (extract_vector_elt %vreg0, Constant<5>),
                     (extract_vector_elt %vreg0, Constant<6>),
                     (extract_vector_elt %vreg0, Constant<7>),
                     %vreg1))

a. We can't build a 256-bit vector efficiently so, we need to split it into
two 128-bit vecs and combine them with VINSERTX128.

b. Operands like (extract_vector_elt (v8f32 %vreg0), Constant<7>) needs to be
split into a VEXTRACTX128 and a further extract_vector_elt from the
resulting 128-bit vector.

c. The extract_vector_elt from b. is lowered into a shuffle to the first
element and a movss.

Depending on the order in which we legalize the BUILD_VECTOR and its
operands[1], buildFromShuffleMostly may be faced with:

(v4f32 (BUILD_VECTOR (extract_vector_elt
                      (vector_shuffle<1,u,u,u> (extract_subvector %vreg0, Constant<4>), undef),
                      Constant<0>),
                     (extract_vector_elt
                      (vector_shuffle<2,u,u,u> (extract_subvector %vreg0, Constant<4>), undef),
                      Constant<0>),
                     (extract_vector_elt
                      (vector_shuffle<3,u,u,u> (extract_subvector %vreg0, Constant<4>), undef),
                      Constant<0>),
                     %vreg1))

In order to figure out the underlying vector and their identity we need to see
through the shuffles.

[1] Note that the order in which operations and their operands are legalized is
only guaranteed in the first iteration of LegalizeDAG.

Fixes <rdar://problem/16296956>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 19:44:16 +00:00
Duncan P. N. Exon Smith
ebb5d29473 Revert "blockfreq: Rewrite BlockFrequencyInfoImpl" (#2)
This reverts commit r206622 and the MSVC fixup in r206626.

Apparently the remotely failing tests are still failing, despite my
attempt to fix the nondeterminism in r206621.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206628 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 17:56:08 +00:00
Duncan P. N. Exon Smith
54850bedf2 Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"
This reverts commit r206556, effectively reapplying commit r206548 and
its fixups in r206549 and r206550.

In an intervening commit I've added target triples to the tests that
were failing remotely [1] (but passing locally).  I'm hoping the mystery
is solved?  I'll revert this again if the tests are still failing
remotely.

[1]: http://bb.pgr.jp/builders/ninja-x64-msvc-RA-centos6/builds/1816

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206622 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 17:22:25 +00:00
Duncan P. N. Exon Smith
1e1954f749 Add some target triples for better determinism
These tests were failing on some buildbots after r206548 (reverted in
r206556), but passing locally.

They were missing target triples, so maybe that's the problem?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206621 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 17:22:19 +00:00
Tim Northover
7b4b261611 AArch64/ARM64: add more NEON tests.
Mostly no testing this time, since they were just wrangling
target-specific intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206613 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 14:54:53 +00:00
Tim Northover
f34a512a68 ARM64: disable generation of .loh directives outside MachO.
Part of PR19455.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206611 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 14:54:46 +00:00
Tim Northover
9cfd368302 ARM64: don't emit .subsections_via_symbols on ELF.
Part of PR19455.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206610 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 14:54:41 +00:00
Tim Northover
1d5a2ad8a6 ARM64: add extra NEG pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206609 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 14:54:35 +00:00
Tim Northover
936285440b AArch64/ARM64: port more AArch64 tests to ARM64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206592 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 13:16:55 +00:00
Tim Northover
753cfe6172 AArch64/ARM64: add non-scalar lowering for more FCVT operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206591 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 13:16:42 +00:00
Tim Northover
7b4b522ec8 AArch64/ARM64: improve spotting of EXT instructions from VECTOR_SHUFFLE.
We couldn't cope if the first mask element was UNDEF before, which
isn't ideal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206588 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 12:50:58 +00:00