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507 Commits

Author SHA1 Message Date
Matt Arsenault
ff71f3dac1 R600: Run private-memory test with and without alloca promote 
The unpromoted path still needs to be tested since we can't
always promote to using LDS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212894 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-13 02:18:06 +00:00
Matt Arsenault
cc6a418600 R600: Add missing tests for some intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212870 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-12 00:36:19 +00:00
Marek Olsak
438e1f2ad8 R600/SI: Use i32 vectors for resources and samplers 
This affects new intrinsics only.

What surprises me is that v32i8 still works.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212831 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-11 17:11:52 +00:00
Marek Olsak
5a35fdcafb R600/SI: add sample and image intrinsics exposing all instruction fields 
We need the intrinsics with offsets, so why not just add them all.
The R128 parameter will also be useful for reducing SGPR usage.
GL_ARB_image_load_store also adds some image GLSL modifiers like "coherent",
so Mesa will probably translate those to slc, glc, etc.

When LLVM 3.5 is released, I'll switch Mesa to these new intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212830 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-11 17:11:46 +00:00
Jan Vesely
865527a09b R600: Implement float to long/ulong 
Use alg. from LegalizeDAG.cpp
Move Expand setting to SIISellowering

v2: Extend existing tests instead of creating new ones
v3: use separate LowerFPTOSINT function
v4: use TargetLowering::expandFP_TO_SINT
    add comment about using FP_TO_SINT for uints

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212773 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-10 22:40:21 +00:00
Matt Arsenault
b730c3d28d Revert "Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine."" 
Don't try to convert the select condition type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212750 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-10 18:21:04 +00:00
NAKAMURA Takumi
5290734b8f Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine." 
This caused miscompilation on, at least, x86-64. SExt(i1 cond) confused other optimizations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212708 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-10 11:37:28 +00:00
Matt Arsenault
425ef825a6 R600/SI: Add support for llvm.convert.{to|from}.fp16 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212676 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-10 03:22:20 +00:00
Matt Arsenault
3e8ed89484 Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine. 
Do this if the truncate is free and the select is legal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212640 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-09 19:12:07 +00:00
Matt Arsenault
0e1619e77c R600: Fix mishandling of load / store chains. 
Fixes various bugs with reordering loads and stores.
Scalarized vector loads weren't collecting the chains
at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212473 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-07 18:34:45 +00:00
Tom Stellard
1378871b1a R600: Promote i64 loads to v2i32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212216 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-02 20:53:54 +00:00
Matt Arsenault
cc0a279949 Revert "Temporary hack to try cleaning extra .s file from bots." 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211967 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-27 23:11:26 +00:00
Matt Arsenault
051cc062b2 Temporary hack to try cleaning extra .s file from bots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211963 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-27 21:43:50 +00:00
David Blaikie
e70cdf9468 Fix test so it doesn't try to write out temporary files into the test tree. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211916 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-27 17:45:43 +00:00
Matt Arsenault
ee5d4a7b73 R600: Don't crash on unhandled instruction in promote alloca 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211906 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-27 16:52:49 +00:00
Matt Arsenault
88a3c72e25 R600: Add some testcases for promote alloca pass. 
More complicated GEPs are skipped. Add some tests to
actually stress this skipping.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211859 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-27 03:55:55 +00:00
Matt Arsenault
3cd8cf6bbd R600/SI: Add FP mode bits to binary. 
The default rounding mode to initialize the mode register needs
to be reported to the runtime. Fill in other bits a kernel
may be interested in setting for future use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211791 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-26 17:22:30 +00:00
Matt Arsenault
b0f5a0e7e7 R600: Fix vector FMA 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211757 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-26 01:28:05 +00:00
Tom Stellard
78d1e95201 R600: Promote i64 stores to v2i32 
Now we need only one 64-bit pattern for stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211643 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-24 23:33:04 +00:00
Matt Arsenault
95eb45c5d9 R600: Fix inconsistency in rsq instructions. 
R600 was using a clamped version of rsq, but SI was not. Add a
new rsq_clamped intrinsic and use them consistently.

It's unclear to me from the documentation what behavior
the R600 instructions have, so I assume they have the legacy behavior
described by the SI documents. For R600, use RECIPSQRT_IEEE
for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also
has RECIPSQRT_FF, which I'm not sure how it fits in here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211637 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-24 22:13:39 +00:00
Matt Arsenault
ed143b7c0c R600/SI: Fix div_scale intrinsic. 
The operand that must match one of the others does matter,
and implement selecting for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211523 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-23 18:28:28 +00:00
Matt Arsenault
9ad2c7ef92 R600: Move add/sub with overflow out of AMDILISelLowering 
Add more tests for these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211517 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-23 18:00:49 +00:00
Matt Arsenault
c4471e9248 R600/SI: Handle i64 sub. 
We can handle it the same way as add

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211514 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-23 18:00:38 +00:00
Jan Vesely
728ea0c91b R600: Add udivrem test 
v2: move < %s to the end of the line
    space after ;
    add v4i32 test

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211476 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-22 21:42:58 +00:00
Tom Stellard
c0bf939e80 R600/SI: Add patterns for ctpop inside a branch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211378 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-20 17:06:11 +00:00
Tom Stellard
61d64acd0c R600/SI: Add a pattern for f32 ftrunc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211377 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-20 17:06:09 +00:00
Tom Stellard
2cda6e8ca6 R600: Expand vector flog2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211376 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-20 17:06:07 +00:00
Tom Stellard
2d245e2da4 R600: Expand vector fexp2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211375 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-20 17:06:05 +00:00
Tom Stellard
538c95179c R600/SI: Add a VALU pattern for i64 xor 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211373 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-20 17:05:57 +00:00
Matt Arsenault
64429cefba R600: Add a few tests I forgot to add. 
These belong with r210827

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211253 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-19 04:24:43 +00:00
Matt Arsenault
d9b35435b8 R600/SI: Add intrinsics for various math instructions. 
These will be used for custom lowering and for library
implementations of various math functions, so it's useful
to expose these as builtins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211247 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-19 01:19:19 +00:00
Matt Arsenault
ce09bda96e R600: Handle fnearbyint 
The difference from rint isn't really relevant here,
so treat them as equivalent. OpenCL doesn't have nearbyint,
so this is sort of pointless other than for completeness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211229 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-18 22:03:45 +00:00
Marek Olsak
f286d63757 R600/SI: add gather4 and getlod intrinsics (v3) 
This contains all the previous patches + getlod support on top of it.
It doesn't use SDNodes anymore, so it's quite small.
It also adds v16i8 to SReg_128, which is used for the sampler descriptor.

Reviewed-by: Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211228 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-18 22:00:29 +00:00
Jan Vesely
52b6c2d6ef R600: Expand vector fceil 
Move fp64 fceil tests to fceil64.ll

v2: rebase

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211194 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-18 17:57:29 +00:00
Matt Arsenault
2b6e6fc1a8 R600/SI: Add intrinsics for brev instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211187 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-18 17:13:57 +00:00
Matt Arsenault
795ae8615f R600/SI: Prettier operand printing for 64-bit ops. 
Copy what is done for 32-bit already so the order is about the same.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211186 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-18 17:13:51 +00:00
Matt Arsenault
debd831223 R600: Implement f64 ftrunc, ffloor and fceil. 
CI has instructions for these, so this fixes them for older hardware.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211183 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-18 17:05:30 +00:00
Matt Arsenault
a5395c03f0 R600: Custom lower f64 frint for pre-CI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211182 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-18 17:05:26 +00:00
Jan Vesely
c32d52df24 R600: Implement 64bit SRA 
v2: Use capitalized variable name

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211159 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-18 12:27:17 +00:00
Jan Vesely
2d06e73d88 R600: Implement 64bit SRL 
v2: use C++ style comment

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211158 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-18 12:27:15 +00:00
Jan Vesely
a64058f3eb R600: Implement 64bit SHL 
v2: Use c++ style comment

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211157 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-18 12:27:13 +00:00
Matt Arsenault
3f1f259c22 R600/SI: Match cttz_zero_undef 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211116 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-17 17:36:27 +00:00
Matt Arsenault
62e378b057 R600/SI: Match ctlz_zero_undef 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211115 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-17 17:36:24 +00:00
Tom Stellard
f56e7678d1 R600: Use LDS and vectors for private memory 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211110 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-17 16:53:14 +00:00
Tom Stellard
bae98b1b45 SelectionDAG: Expand i64 = FP_TO_SINT i32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211108 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-17 16:53:07 +00:00
Matt Arsenault
3c11f69001 R600: Add a rotr testcase I forgot to add 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211002 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-15 21:09:00 +00:00
Matt Arsenault
fa848ccd09 R600: Remove a few more things from AMDILISelLowering 
Try to keep all the setOperationActions for integer ops
together.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211001 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-15 21:08:58 +00:00
Matt Arsenault
e2480a202f R600: Fix assert on vector sdiv 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211000 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-15 21:08:54 +00:00
Matt Arsenault
61bfbc4d96 R600: Report that integer division is expensive. 
Divides by weird constants now emit much better code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210995 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-15 19:48:16 +00:00
NAKAMURA Takumi
e12d893d7a Don't expect tests always crashing. Add "REQUIRES:asserts". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210983 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-15 01:01:11 +00:00