llvm-6502/test/CodeGen/R600
2014-06-17 16:53:07 +00:00
..
32-bit-local-address-space.ll
64bit-kernel-args.ll
128bit-kernel-args.ll
add_i64.ll
add.ll
address-space.ll
and.ll R600: Add more and testcases 2014-06-09 08:36:53 +00:00
anyext.ll
array-ptr-calc-i32.ll
array-ptr-calc-i64.ll
atomic_cmp_swap_local.ll IR: add "cmpxchg weak" variant to support permitted failure. 2014-06-13 14:24:07 +00:00
atomic_load_add.ll R600/SI: Fix backwards names for local atomic instructions. 2014-06-11 18:08:37 +00:00
atomic_load_sub.ll R600/SI: Fix backwards names for local atomic instructions. 2014-06-11 18:08:37 +00:00
basic-branch.ll
basic-loop.ll
bfe_uint.ll
bfi_int.ll
big_alu.ll
bitcast.ll R600/SI: Fix bitcast between v2i32 and f64 2014-06-11 19:31:13 +00:00
bswap.ll R600: Fix selection failure for vector bswap 2014-06-09 16:20:25 +00:00
build_vector.ll
call_fs.ll
call.ll
cayman-loop-bug.ll
cf_end.ll
cf-stack-bug.ll
codegen-prepare-addrmode-sext.ll
combine_vloads.ll
complex-folding.ll
ctpop64.ll R600/SI: Implement i64 ctpop 2014-06-10 19:18:24 +00:00
ctpop.ll R600: Use BCNT_INT for evergreen 2014-06-10 19:18:28 +00:00
cvt_f32_ubyte.ll R600/SI: Use v_cvt_f32_ubyte* instructions 2014-06-11 17:50:44 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
disconnected-predset-break-bug.ll
dot4-folding.ll
elf.ll
elf.r600.ll
extload.ll
extract_vector_elt_i16.ll
fabs.ll
fadd64.ll
fadd.ll
fceil.ll
fcmp64.ll
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.ll
fconst64.ll
fcopysign.f32.ll R600: Handle fcopysign 2014-06-10 19:00:20 +00:00
fcopysign.f64.ll R600: Handle fcopysign 2014-06-10 19:00:20 +00:00
fdiv64.ll
fdiv.ll
fetch-limits.r600.ll
fetch-limits.r700+.ll
ffloor.ll
floor.ll
fma.ll
fmad.ll
fmax.ll
fmin.ll
fmul64.ll
fmul.ll
fmuladd.ll
fneg-fabs.ll
fneg.ll
fp64_to_sint.ll
fp_to_sint_i64.ll SelectionDAG: Expand i64 = FP_TO_SINT i32 2014-06-17 16:53:07 +00:00
fp_to_sint.ll
fp_to_uint.f64.ll
fp_to_uint.ll
fpext.ll
fptrunc.ll
fsqrt.ll
fsub64.ll
fsub.ll
ftrunc.ll
gep-address-space.ll
gv-const-addrspace-fail.ll
gv-const-addrspace.ll Allow aliases to be unnamed_addr. 2014-06-06 01:20:28 +00:00
i8-to-double-to-float.ll
icmp64.ll
icmp-select-sete-reverse-args.ll
imm.ll
indirect-addressing-si.ll
indirect-private-64.ll
infinite-loop-evergreen.ll
infinite-loop.ll
insert_vector_elt_f64.ll
insert_vector_elt.ll
jump-address.ll
kcache-fold.ll
kernel-args.ll
large-alloca.ll Don't expect tests always crashing. Add "REQUIRES:asserts". 2014-06-15 01:01:11 +00:00
large-constant-initializer.ll Don't expect tests always crashing. Add "REQUIRES:asserts". 2014-06-15 01:01:11 +00:00
lds-oqap-crash.ll
lds-output-queue.ll Allow aliases to be unnamed_addr. 2014-06-06 01:20:28 +00:00
lds-size.ll Allow aliases to be unnamed_addr. 2014-06-06 01:20:28 +00:00
legalizedag-bug-expand-setcc.ll
lit.local.cfg Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00
literals.ll
llvm.AMDGPU.barrier.local.ll
llvm.AMDGPU.bfe.i32.ll R600: Try to convert BFE back to standard bit ops when possible. 2014-05-22 18:09:12 +00:00
llvm.AMDGPU.bfe.u32.ll R600: Try to convert BFE back to standard bit ops when possible. 2014-05-22 18:09:12 +00:00
llvm.AMDGPU.bfi.ll
llvm.AMDGPU.bfm.ll
llvm.AMDGPU.cube.ll
llvm.AMDGPU.cvt_f32_ubyte.ll R600/SI: Use v_cvt_f32_ubyte* instructions 2014-06-11 17:50:44 +00:00
llvm.AMDGPU.imad24.ll R600: Expand mad24 for GPUs without it 2014-05-22 18:00:20 +00:00
llvm.AMDGPU.imax.ll
llvm.AMDGPU.imin.ll
llvm.AMDGPU.imul24.ll R600: Expand mul24 for GPUs without it 2014-05-22 18:00:24 +00:00
llvm.AMDGPU.kill.ll
llvm.AMDGPU.mul.ll
llvm.AMDGPU.tex.ll
llvm.AMDGPU.trunc.ll
llvm.AMDGPU.umad24.ll R600: Expand mad24 for GPUs without it 2014-05-22 18:00:20 +00:00
llvm.AMDGPU.umax.ll
llvm.AMDGPU.umin.ll
llvm.AMDGPU.umul24.ll R600: Expand mul24 for GPUs without it 2014-05-22 18:00:24 +00:00
llvm.cos.ll
llvm.exp2.ll
llvm.floor.ll
llvm.pow.ll
llvm.rint.f64.ll
llvm.rint.ll R600: Mostly remove remaining AMDIL intrinsics. 2014-06-12 21:15:44 +00:00
llvm.round.ll
llvm.SI.fs.interp.constant.ll
llvm.SI.imageload.ll
llvm.SI.load.dword.ll
llvm.SI.resinfo.ll
llvm.SI.sample-masked.ll
llvm.SI.sample.ll
llvm.SI.sampled.ll
llvm.SI.sendmsg.ll
llvm.SI.tbuffer.store.ll
llvm.SI.tid.ll
llvm.sin.ll
llvm.sqrt.ll
llvm.trunc.ll
load64.ll
load-i1.ll
load-input-fold.ll
load.ll
load.vec.ll
local-64.ll
local-atomics64.ll R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec* 2014-06-12 08:21:54 +00:00
local-atomics.ll R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec* 2014-06-12 08:21:54 +00:00
local-memory-two-objects.ll Allow aliases to be unnamed_addr. 2014-06-06 01:20:28 +00:00
local-memory.ll Allow aliases to be unnamed_addr. 2014-06-06 01:20:28 +00:00
loop-address.ll
loop-idiom.ll
lshl.ll
lshr.ll
mad_int24.ll
mad_uint24.ll
max-literals.ll
mubuf.ll
mul_int24.ll
mul_uint24.ll
mul.ll R600: Fix test. Using wrong check prefix. 2014-06-05 08:00:36 +00:00
mulhu.ll
no-initializer-constant-addrspace.ll R600: Fix asserts related to constant initializers 2014-06-14 04:26:05 +00:00
or.ll
packetizer.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
predicate-dp4.ll
predicates.ll
private-memory.ll
pv-packing.ll
pv.ll
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600cfg.ll
README
reciprocal.ll
register-count-comments.ll
rotl.i64.ll R600/SI: Fix selection error on i64 rotl / rotr. 2014-06-13 04:00:30 +00:00
rotl.ll R600/SI: Fix selection error on i64 rotl / rotr. 2014-06-13 04:00:30 +00:00
rotr.i64.ll R600: Add a rotr testcase I forgot to add 2014-06-15 21:09:00 +00:00
rotr.ll R600/SI: Fix selection error on i64 rotl / rotr. 2014-06-13 04:00:30 +00:00
rsq.ll R600/SI: Match rsq instructions 2014-06-05 00:15:55 +00:00
rv7x0_count3.ll
salu-to-valu.ll
scalar_to_vector.ll R600/SI: Fix selection failure on scalar_to_vector 2014-06-11 17:40:32 +00:00
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-if-2.ll
schedule-if.ll
schedule-vs-if-nested-loop-failure.ll
schedule-vs-if-nested-loop.ll
sdiv.ll R600: Fix assert on vector sdiv 2014-06-15 21:08:54 +00:00
select64.ll
select-vectors.ll
select.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll
set-dx10.ll
setcc64.ll
setcc-equivalent.ll Revert "SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors" 2014-06-12 16:04:47 +00:00
setcc.ll
seto.ll
setuo.ll
sext-in-reg.ll R600: Try to convert BFE back to standard bit ops when possible. 2014-05-22 18:09:12 +00:00
sgpr-control-flow.ll
sgpr-copy-duplicate-operand.ll
sgpr-copy.ll
shared-op-cycle.ll
shl.ll
si-annotate-cf-assertion.ll
si-lod-bias.ll
si-sgpr-spill.ll
si-vector-hang.ll
sign_extend.ll R600/SI: Handle sign_extend and zero_extend to i64 with patterns. 2014-06-10 18:54:59 +00:00
simplify-demanded-bits-build-pair.ll
sint_to_fp64.ll SelectionDAG: Expand SELECT_CC to SELECT + SETCC 2014-06-10 16:01:22 +00:00
sint_to_fp.ll R600/SI: Fix [s|u]int_to_fp for i1 2014-05-31 06:47:42 +00:00
smrd.ll
sra.ll
srem.ll R600: Remove a few more things from AMDILISelLowering 2014-06-15 21:08:58 +00:00
srl.ll
store-v3i32.ll
store-v3i64.ll
store-vector-ptrs.ll
store.ll
store.r600.ll
structurize1.ll
structurize.ll
sub.ll R600/SI: Keep 64-bit not on SALU 2014-06-09 16:36:31 +00:00
swizzle-export.ll
tex-clause-antidep.ll
texture-input-merge.ll
trunc-store-i1.ll
trunc-vector-store-assertion-failure.ll
trunc.ll
uaddo.ll
udiv.ll
udivrem64.ll R600: Try to convert BFE back to standard bit ops when possible. 2014-05-22 18:09:12 +00:00
uint_to_fp.f64.ll SelectionDAG: Expand SELECT_CC to SELECT + SETCC 2014-06-10 16:01:22 +00:00
uint_to_fp.ll R600/SI: Fix [s|u]int_to_fp for i1 2014-05-31 06:47:42 +00:00
unaligned-load-store.ll
unhandled-loop-condition-assertion.ll
unroll.ll
unsupported-cc.ll
urecip.ll
urem.ll
v1i64-kernel-arg.ll
v_cndmask.ll
valu-i1.ll
vertex-fetch-encoding.ll
vselect64.ll
vselect.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll
work-item-intrinsics.ll
wrong-transalu-pos-fix.ll
xor.ll R600/SI: Keep 64-bit not on SALU 2014-06-09 16:36:31 +00:00
zero_extend.ll

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.