Michael Kuperstein 3dd555171e Add support for parsing the XOR operator in Intel syntax inline assembly. ...

Differential Revision: http://reviews.llvm.org/D10385
Patch by marina.yatsina@intel.com


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239695 91177308-0d34-0410-b5e6-96231b3b80d8

2015-06-14 12:59:45 +00:00

..

AArch64

[AArch64] AsmParser should be case insensitive about accepting vector register names.

2015-06-08 21:32:16 +00:00

AMDGPU

R600 -> AMDGPU rename

2015-06-13 03:28:10 +00:00

ARM

[ARM] Add support for -sp- FPUs and FPU none to TargetParser

2015-06-05 13:31:19 +00:00

AsmParser

Teaching llvm-mc how to understand the defsym command line option. This allows integer-constant symbols to be defined on the command line and used during assembly.

2015-06-07 01:46:24 +00:00

COFF

Revise test to run llc and llvm-mc separately.

2015-05-28 21:49:50 +00:00

Disassembler

[mips][microMIPS] Implement ERET and ERETNC instructions

2015-06-11 10:22:46 +00:00

ELF

Fix a regression in .pop_section.

2015-06-08 20:08:55 +00:00

Hexagon

[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.

2015-06-05 16:00:11 +00:00

MachO

MC: Remove obsolete MachO UseAggressiveSymbolFolding.

2015-06-04 20:27:42 +00:00

Markup

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Mips

Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396).

2015-06-11 10:36:10 +00:00

PowerPC

LLVM support for vector quad bit permute and gather instructions through builtins

2015-06-11 06:21:25 +00:00

Sparc

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SystemZ

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X86

Add support for parsing the XOR operator in Intel syntax inline assembly.

2015-06-14 12:59:45 +00:00