Evan Cheng 0104d9de04 - Assign load / store with shifter op address modes the right itinerary classes. ... - For now, loads of [r, r] addressing mode is the same as the [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should identify the former case and reduce the output latency by 1. - Also identify [r, r << 2] case. This special form of shifter addressing mode is "free". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8		2010-10-28 01:49:06 +00:00
..
Alpha
ARM	- Assign load / store with shifter op address modes the right itinerary classes.	2010-10-28 01:49:06 +00:00
Blackfin
CBackend
CellSPU	Change v64 datalayout in SPU.	2010-10-26 10:45:47 +00:00
CPP
Generic	Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself	2010-07-27 18:02:18 +00:00
MBlaze	Recommit 116986 with capitalization typo fixed.	2010-10-21 03:57:26 +00:00
Mips
MSP430
PowerPC	PowerPC varargs functions store live-in registers on the stack. Make sure we use	2010-10-11 20:43:09 +00:00
PTX	Add test case mov.ll for PTX device function	2010-10-19 13:21:51 +00:00
SPARC
SystemZ	Correct bogus module triple specifications.	2010-08-30 10:48:29 +00:00
Thumb
Thumb2	More accurate estimate / tracking of register pressure.	2010-10-20 22:03:58 +00:00
X86	Fix pastos in handling of AVX cvttsd2si, PR8491.	2010-10-28 00:35:54 +00:00
XCore
thumb2-mul.ll