Akira Hatanaka c0be26909f Mips64 arithmetic and logical instructions with two source registers. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140806 91177308-0d34-0410-b5e6-96231b3b80d8

2011-09-29 20:37:56 +00:00

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Alpha

Convert more tests over to the new atomic instructions.

2011-09-26 21:30:17 +00:00

ARM

LSR: rewrite inner loops only.

2011-09-29 01:33:38 +00:00

Blackfin

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CBackend

Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported

2011-09-26 06:44:27 +00:00

CellSPU

Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.

2011-09-02 10:05:01 +00:00

CPP

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Generic

PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval

2011-09-26 06:13:20 +00:00

MBlaze

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Mips

Mips64 arithmetic and logical instructions with two source registers.

2011-09-29 20:37:56 +00:00

MSP430

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PowerPC

Convert more tests over to the new atomic instructions.

2011-09-26 21:30:17 +00:00

PTX

PTX: Add new patterns for bitconvert and any_extend

2011-09-29 01:13:12 +00:00

SPARC

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SystemZ

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Thumb

Convert more tests to new atomic instructions.

2011-09-26 21:36:10 +00:00

Thumb2

Last batch of test conversions to new atomic instructions.

2011-09-27 00:17:29 +00:00

X86

LSR: rewrite inner loops only.

2011-09-29 01:33:38 +00:00

XCore

Associate a MemOperand with LDWCP nodes introduced during ISel.

2011-09-12 14:43:23 +00:00