llvm-6502/test/CodeGen
2014-09-14 23:39:01 +00:00
..
AArch64 [FastISel][AArch64] Add support for non-native types for logical ops. 2014-09-13 23:46:28 +00:00
ARM [ARM] Add Thumb-2 code size optimization regression test for LSR (register). 2014-09-11 10:45:50 +00:00
CPP
Generic
Hexagon DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range. 2014-08-06 00:21:25 +00:00
Inputs
Mips Replace -use-init-array with -use-ctors. 2014-09-02 13:54:53 +00:00
MSP430 Drop the W postfix on the 16-bit registers. 2014-09-10 06:58:14 +00:00
NVPTX
PowerPC Address comments on r217622 2014-09-12 14:26:36 +00:00
R600 R600/SI: Fix broken check lines 2014-09-14 18:32:05 +00:00
SPARC Provide an implementation of getNoopForMachoTarget for SPARC. 2014-09-11 17:40:51 +00:00
SystemZ
Thumb
Thumb2
X86 llvm/test/CodeGen/X86/vec_shuffle-38.ll: Add explicit -mtriple=x86_64-unknown to avoid incompatibility of win32. 2014-09-14 23:39:01 +00:00
XCore