llvm-6502/lib/CodeGen
Michael J. Spencer 1f6efa3996 Merge System into Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120298 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 18:16:10 +00:00
..
AsmPrinter Merge System into Support. 2010-11-29 18:16:10 +00:00
SelectionDAG Merge System into Support. 2010-11-29 18:16:10 +00:00
AggressiveAntiDepBreaker.cpp
AggressiveAntiDepBreaker.h
Analysis.cpp
AntiDepBreaker.h
BranchFolding.cpp
BranchFolding.h
CalcSpillWeights.cpp
CallingConvLower.cpp In the calling convention logic, ValVT is always a legal type, 2010-11-04 10:49:57 +00:00
CMakeLists.txt Rename ExpandPseudos to ExpandISelPseudos to help clarify its role. 2010-11-18 18:45:06 +00:00
CodeGen.cpp
CodePlacementOpt.cpp
CriticalAntiDepBreaker.cpp Fixes <rdar://problem/8612856>: During postRAsched, the antidependence 2010-11-02 18:16:45 +00:00
CriticalAntiDepBreaker.h Fixes <rdar://problem/8612856>: During postRAsched, the antidependence 2010-11-02 18:16:45 +00:00
DeadMachineInstructionElim.cpp
DwarfEHPrepare.cpp
ELF.h Merge System into Support. 2010-11-29 18:16:10 +00:00
ELFCodeEmitter.cpp
ELFCodeEmitter.h
ELFWriter.cpp
ELFWriter.h
ExpandISelPseudos.cpp Rename ExpandPseudos to ExpandISelPseudos to help clarify its role. 2010-11-18 18:45:06 +00:00
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp Move some more hooks to TargetFrameInfo 2010-11-20 15:59:32 +00:00
IfConversion.cpp Prune includes. 2010-11-06 11:45:59 +00:00
InlineSpiller.cpp When spilling a register defined by an early clobber, make sure that the new 2010-11-15 20:55:49 +00:00
IntrinsicLowering.cpp
LatencyPriorityQueue.cpp
LiveInterval.cpp Teach ConnectedVNInfoEqClasses::Classify to deal with unused values. 2010-10-29 17:37:29 +00:00
LiveIntervalAnalysis.cpp Fix emergency spilling in LiveIntervals::spillPhysRegAroundRegDefsUses. 2010-11-16 19:55:14 +00:00
LiveIntervalUnion.cpp RABasic is nearly functionally complete. There are a few remaining 2010-11-10 19:18:47 +00:00
LiveIntervalUnion.h Check TRI->getReservedRegs because other allocators do it. Even though 2010-11-11 17:46:29 +00:00
LiveRangeEdit.cpp Simplify the LiveRangeEdit::canRematerializeAt() interface a bit. 2010-11-10 01:05:12 +00:00
LiveRangeEdit.h Simplify the LiveRangeEdit::canRematerializeAt() interface a bit. 2010-11-10 01:05:12 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp
LLVMTargetMachine.cpp Change some methods in MCDwarf.cpp to be able to handle an arbitrary 2010-11-19 02:26:16 +00:00
LocalStackSlotAllocation.cpp
LowerSubregs.cpp
MachineBasicBlock.cpp Don't try to split weird critical edges that really aren't: 2010-11-02 00:58:37 +00:00
MachineCSE.cpp Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857. 2010-10-29 23:36:03 +00:00
MachineDominators.cpp
MachineFunction.cpp move the pic base symbol stuff up to MachineFunction 2010-11-14 22:48:15 +00:00
MachineFunctionAnalysis.cpp Attach a GCModuleInfo to a MachineFunction. 2010-10-31 20:38:38 +00:00
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp
MachineLICM.cpp Add a FIXME comment. 2010-11-11 18:08:43 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachineRegisterInfo.cpp
MachineSink.cpp
MachineSSAUpdater.cpp
MachineVerifier.cpp Only avoid the check if we're the last operand before the variable 2010-11-17 00:55:36 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp
PeepholeOptimizer.cpp Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, 2010-11-17 20:13:28 +00:00
PHIElimination.cpp
PHIElimination.h
PostRAHazardRecognizer.cpp
PostRASchedulerList.cpp
PreAllocSplitting.cpp
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp Move more PEI-related hooks to TFI 2010-11-27 23:05:25 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp Merge System into Support. 2010-11-29 18:16:10 +00:00
README.txt
RegAllocBase.h Check TRI->getReservedRegs because other allocators do it. Even though 2010-11-11 17:46:29 +00:00
RegAllocBasic.cpp Namespacify. 2010-11-25 16:42:51 +00:00
RegAllocFast.cpp
RegAllocLinearScan.cpp Don't attempt trivial coalescing for sub-register copies. 2010-11-19 05:45:24 +00:00
RegAllocPBQP.cpp Fix some style issues in PBQP. Patch by David Blaikie. 2010-11-12 05:47:21 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp
RenderMachineFunction.cpp
RenderMachineFunction.h
ScheduleDAG.cpp
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp Two sets of changes. Sorry they are intermingled. 2010-11-03 00:45:17 +00:00
ScheduleDAGInstrs.h
ScheduleDAGPrinter.cpp
ShadowStackGC.cpp
ShrinkWrapping.cpp
SimpleRegisterCoalescing.cpp
SimpleRegisterCoalescing.h
SjLjEHPrepare.cpp Prune includes. 2010-11-06 11:45:59 +00:00
SlotIndexes.cpp Insert two blank SlotIndexes between basic blocks instead of just one. 2010-11-11 00:19:20 +00:00
Spiller.cpp Delete SplittingSpiller. It was not being used by anyone, and it is being 2010-11-11 00:52:44 +00:00
Spiller.h RABasic is nearly functionally complete. There are a few remaining 2010-11-10 19:18:47 +00:00
SplitKit.cpp No need to add liveness that's already there. 2010-11-10 23:56:00 +00:00
SplitKit.h Basic rematerialization during splitting. 2010-11-10 19:31:50 +00:00
Splitter.cpp
Splitter.h
StackProtector.cpp
StackSlotColoring.cpp
StrongPHIElimination.cpp
TailDuplication.cpp
TargetInstrInfoImpl.cpp
TargetLoweringObjectFileImpl.cpp Fixed version of 118639 with an extra assert to catch similar problems 2010-11-09 23:42:07 +00:00
TwoAddressInstructionPass.cpp
UnreachableBlockElim.cpp
VirtRegMap.cpp Remember to resize SpillSlotToUsesMap when allocating an emergency spill slot. 2010-11-16 00:41:01 +00:00
VirtRegMap.h Remember to resize SpillSlotToUsesMap when allocating an emergency spill slot. 2010-11-16 00:41:01 +00:00
VirtRegRewriter.cpp Prune includes. 2010-11-06 11:45:59 +00:00
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.