llvm-6502/test/CodeGen
Pete Cooper 28b0dda32e Handle dead defs in the if converter.
We had code such as this:
  r2 = ...
  t2Bcc

label1:
  ldr ... r2

label2;
  return r2<dead, def>

The if converter was transforming this to
   r2<def> = ...
   return [pred] r2<dead,def>
   ldr <r2, kill>
   return

which fails the machine verifier because the ldr now reads from a dead def.

The fix here detects dead defs in stepForward and passes them back to the caller in the clobbers list.  The caller then clears the dead flag from the def is the value is live.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236660 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-06 22:51:04 +00:00
..
AArch64 CodeGen: move over-zealous assert into actual if statement. 2015-05-06 20:07:38 +00:00
ARM Handle dead defs in the if converter. 2015-05-06 22:51:04 +00:00
BPF
CPP
Generic [Hexagon] r236351 fix does not work on builder configurations yet. 2015-05-01 22:39:20 +00:00
Hexagon IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
Inputs IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
Mips [mips] Generate code for insert/extract operations when using the N64 ABI and MSA. 2015-05-05 10:32:24 +00:00
MSP430
NVPTX
PowerPC [PPC64LE] Adjust vector splats during VSX swap optimization 2015-05-06 15:40:46 +00:00
R600 R600/SI: Add VCC as an implict def of SI_KILL 2015-05-01 03:44:09 +00:00
SPARC
SystemZ [DAGCombiner] Account for getVectorIdxTy() when narrowing vector load 2015-05-05 19:34:10 +00:00
Thumb IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
Thumb2 Thumb2SizeReduction: Check the correct set of registers for LDMIA. 2015-05-05 20:07:10 +00:00
WinEH Flip r236172 testcase RUN option ordering for BSD sed(1). NFC. 2015-04-30 00:07:34 +00:00
X86 [x86] Fix register class of folded load index reg. 2015-05-06 21:37:19 +00:00
XCore IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00