Tom Stellard 7f288b455e R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cpp ... SI doesn't use REGISTER_LOAD anymore, but it was still hitting this code path for 8-bit and 16-bit private loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214566 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-01 21:50:47 +00:00
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AArch64	[FastISel][AArch64] Fold offset into the memory operation.	2014-08-01 19:40:16 +00:00
ARM	[FastISel][ARM] Do not emit stores for undef arguments.	2014-08-01 18:04:14 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips][PR19612] Fix va_arg for big-endian mode.	2014-08-01 09:17:39 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Recognize consecutive memory accesses from intrinsics	2014-08-01 01:02:01 +00:00
R600	R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cpp	2014-08-01 21:50:47 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	MS inline asm: Use memory constraints for functions instead of registers	2014-08-01 20:21:24 +00:00
XCore