Evan Cheng 14a6db8bd9 Initial support for register pressure aware scheduling. The register reduction ... scheduler can go into a "vertical mode" (i.e. traversing up the two-address chain, etc.) when the register pressure is low. This does seem to reduce the number of spills in the cases I've looked at. But with x86, it's no guarantee the performance of the code improves. It can be turned on with -sched-vertically option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28108 91177308-0d34-0410-b5e6-96231b3b80d8		2006-05-04 19:16:39 +00:00
..
Analysis	Implement Transforms/IndVarsSimplify/complex-scev.ll, a case where we didn't	2006-04-26 18:34:07 +00:00
Archive
AsmParser	Make sure CVS versions of yacc and lex files get distributed.	2006-04-12 20:57:05 +00:00
Bytecode	use isValidOperands instead of duplicating checks	2006-04-08 04:09:19 +00:00
CodeGen	Initial support for register pressure aware scheduling. The register reduction	2006-05-04 19:16:39 +00:00
Debugger	Add the README files to the distribution.	2006-04-13 06:39:24 +00:00
ExecutionEngine	minor cleanups, no functionality change	2006-05-03 18:55:56 +00:00
Linker	Add shufflevector support	2006-04-08 01:19:47 +00:00
Support	Fix PR743: emit -help output of a tool to cout, not cerr.	2006-04-28 05:36:25 +00:00
System	Mingw32 patches supplied by Anton Korobeynikov.	2006-04-29 18:41:44 +00:00
Target	Remove and simplify some more machineinstr/machineoperand stuff.	2006-05-04 18:16:01 +00:00
Transforms	Fix Transforms/InstCombine/2006-05-04-DemandedBitCrash.ll	2006-05-04 17:33:35 +00:00
VMCore	Add assertions that verify that the actual arguments to a call or invoke match	2006-05-03 00:48:22 +00:00
Makefile