Nate Begeman 14e2cf62f4 Properly split f32 and f64 into separate register classes for scalar sse fp ... fixing a bunch of nasty hackery git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23735 91177308-0d34-0410-b5e6-96231b3b80d8		2005-10-14 22:06:00 +00:00
..
Alpha	This seems useful from the original patch that added the function. If there is a reason it is not useful on a RISC type target, let me know and I will pull it out	2005-10-09 20:11:35 +00:00
CBackend
IA64	Fix CodeGen/Generic/bool-to-double.ll	2005-10-07 04:50:48 +00:00
PowerPC	Remove an unnecsesary file. PPC32 and PPC64 share architected registers.	2005-10-14 18:58:46 +00:00
Skeleton
Sparc	silence some warnings	2005-10-05 17:15:09 +00:00
SparcV8	silence some warnings	2005-10-05 17:15:09 +00:00
SparcV9	silence a warning	2005-10-02 16:27:59 +00:00
X86	Properly split f32 and f64 into separate register classes for scalar sse fp	2005-10-14 22:06:00 +00:00
Makefile
MRegisterInfo.cpp	Rename MRegisterDesc -> TargetRegisterDesc for consistency	2005-09-30 17:49:27 +00:00
SubtargetFeature.cpp
Target.td	Pull DAG ISel generation nodes out of the PowerPC backend to where they	2005-10-10 06:00:30 +00:00
TargetData.cpp
TargetFrameInfo.cpp
TargetInstrInfo.cpp
TargetMachine.cpp
TargetMachineRegistry.cpp
TargetSchedInfo.cpp
TargetSelectionDAG.td	add the integer truncate/extension operations	2005-10-14 06:40:20 +00:00
TargetSubtarget.cpp