Richard Sandiford 16277c4698 [SystemZ] Add NC, OC and XC ... For now these are just used to handle scalar ANDs, ORs and XORs in which all operands are memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190041 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-05 10:36:45 +00:00
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AArch64	Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:	2013-09-04 09:28:24 +00:00
ARM	[ARMv8] Add MC support for the new load/store acquire/release instructions.	2013-08-27 17:38:16 +00:00
Mips	[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.	2013-08-28 00:55:15 +00:00
SystemZ	[SystemZ] Add NC, OC and XC	2013-09-05 10:36:45 +00:00
X86	Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode.	2013-08-30 21:19:48 +00:00
XCore	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00