6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-24 09:29:42 +00:00
Code Issues Projects Releases Wiki Activity
18fc42ab12
llvm-6502/test/MC/Mips/mips32r6
History
Toma Tabacu f28b151b52 [mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction. 
Summary:
This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58".
This should work for all MIPS ISAs.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8284

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232473 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-17 13:17:44 +00:00
..
invalid-mips1-wrong-error.s [mips] Improve the error messages given by MipsAsmParser. 2014-09-16 15:00:52 +00:00
invalid-mips1.s [mips] Marked the ADDi instruction aliases as not available in Mips32R6 and Mips64R6. 2014-09-16 09:26:09 +00:00
invalid-mips2-wrong-error.s [mips] Add support for COP1's Branch-On-Cond-Likely instructions 2014-10-17 14:08:28 +00:00
invalid-mips2.s [mips] Add support for COP1's Branch-On-Cond-Likely instructions 2014-10-17 14:08:28 +00:00
invalid-mips4-wrong-error.s [mips] Add support for COP1's Branch-On-Cond-Likely instructions 2014-10-17 14:08:28 +00:00
invalid-mips4.s [mips] Add support for COP1's Branch-On-Cond-Likely instructions 2014-10-17 14:08:28 +00:00
invalid-mips5-wrong-error.s [mips] Improve the error messages given by MipsAsmParser. 2014-09-16 15:00:52 +00:00
invalid-mips5.s [mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 2014-06-12 14:19:28 +00:00
invalid-mips32-wrong-error.s [mips] Add support for COP1's Branch-On-Cond-Likely instructions 2014-10-17 14:08:28 +00:00
invalid-mips32.s [mips] Add support for COP1's Branch-On-Cond-Likely instructions 2014-10-17 14:08:28 +00:00
invalid-mips32r2.s [mips][mips64r6] madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not available on MIPS32r6/MIPS64r6 2014-06-12 11:04:18 +00:00
invalid.s [mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates rather than 16-bit in MIPS32r6/MIPS64r6 2014-06-16 10:00:45 +00:00
relocations.s [mips][mips64r6] Add R_MIPS_PC19_S2 2014-06-12 12:40:00 +00:00
valid-xfail.s [mips][mips64r6] Add b[on]vc 2014-05-22 11:23:21 +00:00
valid.s [mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction. 2015-03-17 13:17:44 +00:00