Mihai Popa 2248cf5906 This is a simple patch that changes RRX and RRXS to accept all registers as operands. ... According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8		2013-06-05 13:23:51 +00:00
..
arm-tests.txt	ARM: Correct printing of pre-indexed operands.	2013-04-12 18:47:25 +00:00
arm-thumb-trustzone.txt	ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.	2013-04-10 12:08:35 +00:00
arm-trustzone.txt	ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.	2013-04-10 12:08:35 +00:00
basic-arm-instructions.txt	This is a simple patch that changes RRX and RRXS to accept all registers as operands.	2013-06-05 13:23:51 +00:00
fp-encoding.txt	ARM: add fstmx and fldmx instructions for assembly	2013-05-31 15:55:51 +00:00
hex-immediates.txt	Added a option to the disassembler to print immediates as hex.	2012-12-05 18:13:19 +00:00
invalid-Bcc-thumb.txt
invalid-BFI-arm.txt
invalid-CPS2p-arm.txt
invalid-CPS3p-arm.txt
invalid-DMB-thumb.txt
invalid-DSB-arm.txt
invalid-FSTMX-arm.txt	ARM: add fstmx and fldmx instructions for assembly	2013-05-31 15:55:51 +00:00
invalid-hint-arm.txt	ARM: Fix encoding of hint instruction for Thumb.	2013-04-26 17:54:54 +00:00
invalid-hint-thumb.txt	ARM: Fix encoding of hint instruction for Thumb.	2013-04-26 17:54:54 +00:00
invalid-IT-CBNZ-thumb.txt
invalid-IT-CC15.txt
invalid-IT-thumb.txt
invalid-LDC-form-arm.txt
invalid-LDM-thumb.txt
invalid-LDR_POST-arm.txt	s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL.	2013-04-30 09:00:12 +00:00
invalid-LDR_PRE-arm.txt
invalid-LDRB_POST-arm.txt
invalid-LDRD_PRE-thumb.txt
invalid-LDRrs-arm.txt
invalid-MCR-arm.txt
invalid-MOVr-arm.txt
invalid-MOVs-arm.txt
invalid-MOVs-LSL-arm.txt
invalid-MOVTi16-arm.txt
invalid-MRRC2-arm.txt
invalid-MSRi-arm.txt
invalid-RFEorLDMIA-arm.txt
invalid-SBFX-arm.txt
invalid-SMLAD-arm.txt
invalid-SRS-arm.txt
invalid-STMIA_UPD-thumb.txt
invalid-SXTB-arm.txt
invalid-t2Bcc-thumb.txt
invalid-t2LDRBT-thumb.txt
invalid-t2LDREXD-thumb.txt
invalid-t2LDRSHi8-thumb.txt
invalid-t2LDRSHi12-thumb.txt
invalid-t2PUSH-thumb.txt
invalid-t2STR_POST-thumb.txt
invalid-t2STRD_PRE-thumb.txt
invalid-t2STREXB-thumb.txt
invalid-t2STREXD-thumb.txt
invalid-UMAAL-arm.txt
invalid-VEXTd-arm.txt	ARM: fix VEXT encoding corner case	2013-05-31 13:47:25 +00:00
invalid-VLD1DUPq8_UPD-arm.txt	Diagnose invalid alignments on duplicating VLDn instructions.	2012-09-06 15:27:12 +00:00
invalid-VLD1LNd32_UPD-thumb.txt
invalid-VLD3DUPd32_UPD-thumb.txt
invalid-VLD4DUPd32_UPD-thumb.txt	Diagnose invalid alignments on duplicating VLDn instructions.	2012-09-06 15:27:12 +00:00
invalid-VLD4LNd32_UPD-thumb.txt
invalid-VLDMSDB_UPD-arm.txt
invalid-VQADD-arm.txt	Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).	2013-05-20 14:42:43 +00:00
invalid-VST1d8Twb_register-thumb.txt	Make ARMAsmParser accept the correct alignment specifier syntax in instructions.	2013-02-14 14:46:12 +00:00
invalid-VST1LNd32_UPD-thumb.txt
invalid-VST2b32_UPD-arm.txt	VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).	2013-05-20 14:57:05 +00:00
invalid-VST4LNd32_UPD-thumb.txt
invalid-VST-arm.txt	VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).	2013-05-20 14:57:05 +00:00
ldrd-armv4.txt
lit.local.cfg
marked-up-thumb.txt	ARM: Better disassembly for pc-relative LDR.	2012-10-30 01:04:51 +00:00
memory-arm-instructions.txt
neon-tests.txt	Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.	2013-02-22 10:01:33 +00:00
neon.txt	Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.	2013-02-22 10:01:33 +00:00
neont2.txt	Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.	2013-02-22 10:01:33 +00:00
neont-VLD-reencoding.txt	Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.	2013-02-22 10:01:33 +00:00
neont-VST-reencoding.txt	Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.	2013-02-22 10:01:33 +00:00
thumb1.txt	ARM: Better disassembly for pc-relative LDR.	2012-10-30 01:04:51 +00:00
thumb2.txt	Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set.	2013-03-28 19:22:28 +00:00
thumb-MSR-MClass.txt
thumb-printf.txt	ARM: Better disassembly for pc-relative LDR.	2012-10-30 01:04:51 +00:00
thumb-tests.txt	ARM: Better disassembly for pc-relative LDR.	2012-10-30 01:04:51 +00:00
unpredictable-ADC-arm.txt
unpredictable-ADDREXT3-arm.txt
unpredictable-AExtI-arm.txt
unpredictable-AI1cmp-arm.txt
unpredictable-BFI.txt	Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst	2012-11-29 23:47:11 +00:00
unpredictable-LDR-arm.txt
unpredictable-LDRD-arm.txt
unpredictable-LSL-regform.txt
unpredictable-MRRC2-arm.txt
unpredictable-MRS-arm.txt
unpredictable-MUL-arm.txt
unpredictable-RSC-arm.txt
unpredictable-SEL-arm.txt
unpredictable-SHADD16-arm.txt
unpredictable-SSAT-arm.txt
unpredictable-STRBrs-arm.txt
unpredictable-swp-arm.txt
unpredictable-UQADD8-arm.txt
unpredictables-thumb.txt
vfp4.txt