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128bit-kernel-args.ll
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add.v4i32.ll
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alu-split.ll
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R600: Fix last ALU of a clause being emitted in a separate clause
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2013-04-03 18:24:47 +00:00 |
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and.v4i32.ll
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dagcombiner-bug-illegal-vec4-int-to-fp.ll
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disconnected-predset-break-bug.ll
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R600: Add support for native control flow
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2013-04-01 21:48:05 +00:00 |
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fabs.ll
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fadd.ll
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fadd.v4f32.ll
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fcmp-cnd.ll
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fcmp-cnde-int-args.ll
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R600: Improve custom lowering of select_cc
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2013-03-08 15:37:09 +00:00 |
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fcmp.ll
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R600: Change operation action from Custom to Expand for BR_CC
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2013-03-08 15:37:07 +00:00 |
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fdiv.v4f32.ll
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floor.ll
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fmad.ll
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fmax.ll
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fmin.ll
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fmul.ll
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fmul.v4f32.ll
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fsub.ll
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fsub.v4f32.ll
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i8_to_double_to_float.ll
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icmp-select-sete-reverse-args.ll
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Test case hygiene.
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2013-03-09 18:25:40 +00:00 |
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imm.ll
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R600/SI: Add support for buffer stores v2
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2013-04-05 23:31:51 +00:00 |
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jump_address.ll
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R600: Take export into account when computing cf address
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2013-04-04 13:59:59 +00:00 |
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kcache-fold.ll
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R600: Emit CF_ALU and use true kcache register.
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2013-04-01 21:47:42 +00:00 |
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legalizedag-bug-expand-setcc.ll
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LegalizeDAG: Respect the result of TLI.getBooleanContents() when expanding SETCC
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2013-03-08 15:37:02 +00:00 |
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lit.local.cfg
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literals.ll
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Test case hygiene.
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2013-03-09 18:25:40 +00:00 |
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llvm.AMDGPU.mul.ll
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llvm.AMDGPU.tex.ll
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llvm.AMDGPU.trunc.ll
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llvm.cos.ll
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llvm.pow.ll
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R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730
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2013-03-22 15:24:16 +00:00 |
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llvm.SI.fs.interp.constant.ll
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R600/SI: Add processor types for each SI variant
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2013-04-05 23:31:35 +00:00 |
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llvm.SI.sample.ll
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R600/SI: dynamical figure out the reg class of MIMG
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2013-04-10 08:39:16 +00:00 |
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llvm.sin.ll
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load.constant_addrspace.f32.ll
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load.i8.ll
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loop-adress.ll
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R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addr
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2013-04-10 13:29:20 +00:00 |
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lshl.ll
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R600/SI: Add processor types for each SI variant
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2013-04-05 23:31:35 +00:00 |
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lshr.ll
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R600/SI: Add processor types for each SI variant
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2013-04-05 23:31:35 +00:00 |
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mulhu.ll
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R600/SI: Add processor types for each SI variant
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2013-04-05 23:31:35 +00:00 |
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predicates.ll
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R600: Add support for native control flow
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2013-04-01 21:48:05 +00:00 |
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reciprocal.ll
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schedule-fs-loop-nested-if.ll
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llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts.
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2013-03-11 23:16:30 +00:00 |
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schedule-fs-loop-nested.ll
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llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts.
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2013-03-11 23:16:30 +00:00 |
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schedule-fs-loop.ll
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llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts.
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2013-03-11 23:16:30 +00:00 |
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schedule-if-2.ll
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llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts.
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2013-03-11 23:16:30 +00:00 |
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schedule-if.ll
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llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts.
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2013-03-11 23:16:30 +00:00 |
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schedule-vs-if-nested-loop.ll
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llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts.
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2013-03-11 23:16:30 +00:00 |
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sdiv.ll
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selectcc_cnde_int.ll
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selectcc_cnde.ll
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selectcc-icmp-select-float.ll
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selectcc-opt.ll
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R600: Optimize another selectcc case
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2013-03-08 15:37:11 +00:00 |
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set-dx10.ll
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setcc.v4i32.ll
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seto.ll
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R600/SI: Add processor types for each SI variant
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2013-04-05 23:31:35 +00:00 |
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setuo.ll
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R600/SI: Add processor types for each SI variant
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2013-04-05 23:31:35 +00:00 |
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short-args.ll
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store.ll
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R600/SI: Add support for buffer stores v2
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2013-04-05 23:31:51 +00:00 |
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store.v4f32.ll
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store.v4i32.ll
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udiv.v4i32.ll
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unsupported-cc.ll
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urecip.ll
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R600/SI: Add pattern for AMDGPUurecip
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2013-04-10 17:17:56 +00:00 |
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urem.v4i32.ll
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vec4-expand.ll
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