llvm-6502/lib/CodeGen
Benjamin Kramer 1a50a12b43 Prefer SmallVector::append/insert over push_back loops.
Same functionality, but hoists the vector growth out of the loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229500 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-17 15:29:18 +00:00
..
AsmPrinter AsmPrinter: Use DIExpression default constructor, NFC 2015-02-17 02:42:45 +00:00
SelectionDAG Prefer SmallVector::append/insert over push_back loops. 2015-02-17 15:29:18 +00:00
AggressiveAntiDepBreaker.cpp Correct the AggressiveAntiDepBreaker's handling of subregisters defining super registers 2015-01-28 14:44:14 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp Add assertions for out of bound index in ComputeLinearIndex 2015-01-14 05:38:48 +00:00
AntiDepBreaker.h
AtomicExpandPass.cpp Migrate AtomicExpandPass and DwarfEHPrepare to using a Function-ized getSubtargetImpl. 2015-01-27 01:04:42 +00:00
BasicTargetTransformInfo.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
BranchFolding.cpp CodeGen: Canonicalize access to function attributes, NFC 2015-02-14 01:44:41 +00:00
BranchFolding.h
CalcSpillWeights.cpp Update SetVector to rely on the underlying set's insert to return a pair<iterator, bool> 2014-11-19 07:49:26 +00:00
CallingConvLower.cpp musttail: Only set the inreg flag for fastcall and vectorcall 2015-01-12 23:28:23 +00:00
CMakeLists.txt Use ADDITIONAL_HEADER_DIRS in all LLVM CMake projects. 2015-02-11 03:28:02 +00:00
CodeGen.cpp [PM] Change the core design of the TTI analysis to use a polymorphic 2015-01-31 03:43:40 +00:00
CodeGenPrepare.cpp CodeGen: Canonicalize access to function attributes, NFC 2015-02-14 01:44:41 +00:00
CriticalAntiDepBreaker.cpp
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp Add the llvm.frameallocate and llvm.recoverframeallocation intrinsics 2015-01-13 00:48:10 +00:00
DFAPacketizer.cpp
DwarfEHPrepare.cpp EHPrepare: Remove leftover initialization code for DomTrees. 2015-01-29 13:26:50 +00:00
EarlyIfConversion.cpp The subtarget is cached on the MachineFunction. Access it directly. 2015-01-27 07:31:29 +00:00
EdgeBundles.cpp
ErlangGC.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
ExecutionDepsFix.cpp ExecutionDepsFix: Correctly handle wide registers. 2014-12-17 19:13:47 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp
ForwardControlFlowIntegrity.cpp [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
GCMetadata.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
GCMetadataPrinter.cpp clang-format all the GC related files (NFC) 2015-01-16 23:16:12 +00:00
GCRootLowering.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
GCStrategy.cpp Revert GCStrategy ownership changes 2015-01-26 18:26:35 +00:00
GlobalMerge.cpp [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
IfConversion.cpp The subtarget is cached on the MachineFunction. Access it directly. 2015-01-27 07:31:29 +00:00
InlineSpiller.cpp Prefer SmallVector::append/insert over push_back loops. 2015-02-17 15:29:18 +00:00
InterferenceCache.cpp
InterferenceCache.h
IntrinsicLowering.cpp
JumpInstrTables.cpp [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
LatencyPriorityQueue.cpp
LexicalScopes.cpp AsmPrinter: Stop creating DebugLocs 2015-02-17 00:02:27 +00:00
LiveDebugVariables.cpp [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
LiveDebugVariables.h [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
LiveInterval.cpp [LiveIntervalAnalysis] Speed up creation of live ranges for physical registers 2015-02-06 18:42:41 +00:00
LiveIntervalAnalysis.cpp [LiveIntervalAnalysis] Speed up creation of live ranges for physical registers 2015-02-06 18:42:41 +00:00
LiveIntervalUnion.cpp LiveIntervalUnion: Allow specification of liverange when unifying/extracting. 2014-12-10 01:12:59 +00:00
LivePhysRegs.cpp
LiveRangeCalc.cpp LiveInterval: Introduce createMainRangeFromSubranges(). 2014-12-24 02:11:51 +00:00
LiveRangeCalc.h LiveRangeCalc: Rewrite subrange calculation 2014-12-16 04:03:38 +00:00
LiveRangeEdit.cpp MachineRegisterInfo can access TII off of the MachineFunction's 2015-01-27 01:15:16 +00:00
LiveRegMatrix.cpp [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
LiveStackAnalysis.cpp Move register class name strings to a single array in MCRegisterInfo to reduce static table size and number of relocation entries. 2014-11-17 05:50:14 +00:00
LiveVariables.cpp
LLVMBuild.txt
LLVMTargetMachine.cpp [PM] Remove the old 'PassManager.h' header file at the top level of 2015-02-13 10:01:29 +00:00
LocalStackSlotAllocation.cpp [Statepoints 2/4] Statepoint infrastructure for garbage collection: MI & x86-64 Backend 2014-12-01 22:52:56 +00:00
MachineBasicBlock.cpp The leak detector is dead, long live asan and valgrind. 2014-12-22 13:00:36 +00:00
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp CodeGen: Canonicalize access to function attributes, NFC 2015-02-14 01:44:41 +00:00
MachineBranchProbabilityInfo.cpp
MachineCombiner.cpp CodeGen: Canonicalize access to function attributes, NFC 2015-02-14 01:44:41 +00:00
MachineCopyPropagation.cpp
MachineCSE.cpp MachineCSE: Clear dead-def flag on CSE. 2015-02-04 19:35:16 +00:00
MachineDominanceFrontier.cpp [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
MachineDominators.cpp
MachineFunction.cpp CodeGen: Canonicalize access to function attributes, NFC 2015-02-14 01:44:41 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
MachineFunctionPrinterPass.cpp Rename argument strings of codegen passes to avoid collisions with command line 2014-12-13 04:52:04 +00:00
MachineInstr.cpp Move DebugLocs around instead of copying. 2015-02-07 12:28:15 +00:00
MachineInstrBundle.cpp Update SetVector to rely on the underlying set's insert to return a pair<iterator, bool> 2014-11-19 07:49:26 +00:00
MachineLICM.cpp Small cleanup of MachineLICM.cpp 2015-02-05 22:39:46 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp Unify the two EH personality classification routines I wrote 2015-02-14 00:21:02 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegionInfo.cpp [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
MachineRegisterInfo.cpp MachineRegisterInfo can access TII off of the MachineFunction's 2015-01-27 01:15:16 +00:00
MachineScheduler.cpp The subtarget is cached on the MachineFunction. Access it directly. 2015-01-27 07:31:29 +00:00
MachineSink.cpp Use DomTree in MachineSink to sink over diamonds. 2014-12-04 10:36:42 +00:00
MachineSSAUpdater.cpp
MachineTraceMetrics.cpp The subtarget is cached on the MachineFunction. Access it directly. 2015-01-27 07:31:29 +00:00
MachineVerifier.cpp Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. 2015-02-04 00:02:59 +00:00
Makefile
module.modulemap
OcamlGC.cpp Revert GCStrategy ownership changes 2015-01-26 18:26:35 +00:00
OptimizePHIs.cpp Update SetVector to rely on the underlying set's insert to return a pair<iterator, bool> 2014-11-19 07:49:26 +00:00
Passes.cpp [PM] Remove the old 'PassManager.h' header file at the top level of 2015-02-13 10:01:29 +00:00
PeepholeOptimizer.cpp Peephole opt needs optimizeSelect() to keep track of newly created MIs 2015-01-13 07:07:13 +00:00
PHIElimination.cpp Update SetVector to rely on the underlying set's insert to return a pair<iterator, bool> 2014-11-19 07:49:26 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp The subtarget is cached on the MachineFunction. Access it directly. 2015-01-27 07:31:29 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp [X86] Convert esp-relative movs of function arguments to pushes, step 2 2015-02-01 16:56:04 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp [RegAllocGreedy] Introduce a late pass to repair broken hints. 2015-01-08 01:16:39 +00:00
RegAllocBase.h [RegAllocGreedy] Introduce a late pass to repair broken hints. 2015-01-08 01:16:39 +00:00
RegAllocBasic.cpp
RegAllocFast.cpp [RegAllocFast] Handle implicit definitions conservatively. 2014-12-03 23:38:08 +00:00
RegAllocGreedy.cpp [RegAllocGreedy] Introduce a late pass to repair broken hints. 2015-01-08 01:16:39 +00:00
RegAllocPBQP.cpp Prefer SmallVector::append/insert over push_back loops. 2015-02-17 15:29:18 +00:00
RegisterClassInfo.cpp Silence more static analyzer warnings. 2014-12-15 18:48:43 +00:00
RegisterCoalescer.cpp RegisterCoalescer: Don't rematerialize subregister definitions. 2015-02-16 22:05:17 +00:00
RegisterCoalescer.h
RegisterPressure.cpp
RegisterScavenging.cpp
ScheduleDAG.cpp Replace some uses of getSubtargetImpl with the cached version 2015-01-27 08:48:42 +00:00
ScheduleDAGInstrs.cpp Bugfix for missed dependency from store to load in buildSchedGraph(). 2015-02-10 13:03:32 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp
ShadowStackGC.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
ShadowStackGCLowering.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
SjLjEHPrepare.cpp Replace some uses of getSubtargetImpl with the cached version 2015-01-27 08:48:42 +00:00
SlotIndexes.cpp
Spiller.h [RegAlloc] Kill off the trivial spiller - nobody is using it any more. 2014-11-06 19:12:38 +00:00
SpillPlacement.cpp
SpillPlacement.h
SplitKit.cpp LiveIntervalAnalysis: Factor out code to update liveness on vreg def removal 2015-01-21 19:02:30 +00:00
SplitKit.h
StackColoring.cpp IR: Split Metadata from Value 2014-12-09 18:38:53 +00:00
StackMapLivenessAnalysis.cpp [StackMaps] Allow the target to pre-process the live-out mask 2015-01-13 17:47:59 +00:00
StackMaps.cpp Move DataLayout back to the TargetMachine from TargetSubtargetInfo 2015-01-26 19:03:15 +00:00
StackProtector.cpp CodeGen: Canonicalize access to function attributes, NFC 2015-02-14 01:44:41 +00:00
StackSlotColoring.cpp
StatepointExampleGC.cpp Revert GCStrategy ownership changes 2015-01-26 18:26:35 +00:00
TailDuplication.cpp CodeGen: Canonicalize access to function attributes, NFC 2015-02-14 01:44:41 +00:00
TargetFrameLoweringImpl.cpp [X86] Convert esp-relative movs of function arguments to pushes, step 2 2015-02-01 16:56:04 +00:00
TargetInstrInfo.cpp Move DataLayout back to the TargetMachine from TargetSubtargetInfo 2015-01-26 19:03:15 +00:00
TargetLoweringBase.cpp Move DataLayout back to the TargetMachine from TargetSubtargetInfo 2015-01-26 19:03:15 +00:00
TargetLoweringObjectFileImpl.cpp Fix quoting of #pragma comment for MS compat, LLVM part. 2015-02-16 11:57:17 +00:00
TargetOptionsImpl.cpp Migrate ABIName to MCTargetOptions so that it can be shared between 2015-01-14 00:50:31 +00:00
TargetRegisterInfo.cpp Introduce register dump helper 2014-11-19 19:46:11 +00:00
TargetSchedule.cpp
TwoAddressInstructionPass.cpp Replace some uses of getSubtargetImpl with the cached version 2015-01-27 08:48:42 +00:00
UnreachableBlockElim.cpp Replace size method call of containers to empty method where appropriate 2015-01-15 11:41:30 +00:00
VirtRegMap.cpp LiveInterval: Use range based for loops for subregister ranges. 2014-12-11 00:59:06 +00:00
WinEHPrepare.cpp Don't promote asynch EH invokes of nounwind functions to calls 2015-02-11 01:23:16 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.