llvm-6502/test/CodeGen/Hexagon
Jakob Stoklund Olesen 4ad27eda29 Infer instruction properties from single-instruction patterns.
Previously, instructions without a primary patterns wouldn't get their
properties inferred. Now, we use all single-instruction patterns for
inference, including 'def : Pat<>' instances.

This causes a lot of instruction flags to change.

- Many instructions no longer have the UnmodeledSideEffects flag because
  their flags are now inferred from a pattern.

- Instructions with intrinsics will get a mayStore flag if they already
  have UnmodeledSideEffects and a mayLoad flag if they already have
  mayStore. This is because intrinsics properties are linear.

- Instructions with atomic_load patterns get a mayStore flag because
  atomic loads can't be reordered. The correct workaround is to create
  pseudo-instructions instead of using normal loads. PR13693.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 22:46:53 +00:00
..
args.ll Enable all Hexagon tests. 2012-05-15 16:13:12 +00:00
combine.ll Enable all Hexagon tests. 2012-05-15 16:13:12 +00:00
convertdptoint.ll Hexagon V5 FP Support. 2012-05-10 20:20:25 +00:00
convertdptoll.ll Hexagon V5 FP Support. 2012-05-10 20:20:25 +00:00
convertsptoint.ll Hexagon V5 FP Support. 2012-05-10 20:20:25 +00:00
convertsptoll.ll Hexagon V5 FP Support. 2012-05-10 20:20:25 +00:00
dadd.ll Hexagon V5 FP Support. 2012-05-10 20:20:25 +00:00
dmul.ll Hexagon V5 FP Support. 2012-05-10 20:20:25 +00:00
double.ll Enable all Hexagon tests. 2012-05-15 16:13:12 +00:00
doubleconvert-ieee-rnd-near.ll Hexagon V5 FP Support. 2012-05-10 20:20:25 +00:00
dsub.ll Hexagon V5 FP Support. 2012-05-10 20:20:25 +00:00
dualstore.ll Revert 156634 upon request until code improvement changes are made. 2012-05-14 19:35:42 +00:00
fadd.ll Hexagon V5 FP Support. 2012-05-10 20:20:25 +00:00
fcmp.ll Hexagon V5 FP Support. 2012-05-10 20:20:25 +00:00
float.ll Enable all Hexagon tests. 2012-05-15 16:13:12 +00:00
floatconvert-ieee-rnd-near.ll Enable all Hexagon tests. 2012-05-15 16:13:12 +00:00
fmul.ll Hexagon V5 FP Support. 2012-05-10 20:20:25 +00:00
frame.ll Enable all Hexagon tests. 2012-05-15 16:13:12 +00:00
fsub.ll Hexagon V5 FP Support. 2012-05-10 20:20:25 +00:00
fusedandshift.ll Support for target dependent Hexagon VLIW packetizer. 2012-05-03 21:52:53 +00:00
lit.local.cfg Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu 2012-03-25 09:02:19 +00:00
macint.ll Support for target dependent Hexagon VLIW packetizer. 2012-05-03 21:52:53 +00:00
mpy.ll Enable all Hexagon tests. 2012-05-15 16:13:12 +00:00
newvaluejump2.ll Support for Hexagon feature, New Value Jump. 2012-05-12 05:10:30 +00:00
newvaluejump.ll Infer instruction properties from single-instruction patterns. 2012-08-24 22:46:53 +00:00
newvaluestore.ll Infer instruction properties from single-instruction patterns. 2012-08-24 22:46:53 +00:00
opt-fabs.ll Add test triples to fix win32 failures. Revert workaround from r161292. 2012-08-08 20:31:37 +00:00
opt-fneg.ll Hexagon V5 FP Support. 2012-05-10 20:20:25 +00:00
simpletailcall.ll [Hexagon] Don't mark callee saved registers as clobbered by a tail call 2012-08-13 19:54:01 +00:00
static.ll Enable all Hexagon tests. 2012-05-15 16:13:12 +00:00
struct_args_large.ll Enable all Hexagon tests. 2012-05-15 16:13:12 +00:00
struct_args.ll Enable all Hexagon tests. 2012-05-15 16:13:12 +00:00
vaddh.ll Enable all Hexagon tests. 2012-05-15 16:13:12 +00:00