Jyotsna Verma 1d3d2c57f5 Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle ... zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174429 91177308-0d34-0410-b5e6-96231b3b80d8		2013-02-05 19:20:45 +00:00
..
absaddr-store.ll	Hexagon: Use multiclass for absolute addressing mode stores.	2013-02-05 18:15:34 +00:00
args.ll
cmp_pred_reg.ll	Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle	2013-02-05 19:20:45 +00:00
cmp_pred.ll	Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle	2013-02-05 19:20:45 +00:00
cmp-to-genreg.ll	Hexagon: Add V4 compare instructions. Enable relationship mapping	2013-02-05 16:42:24 +00:00
cmp-to-predreg.ll	Hexagon: Add V4 compare instructions. Enable relationship mapping	2013-02-05 16:42:24 +00:00
cmpb_pred.ll	Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle	2013-02-05 19:20:45 +00:00
combine_ir.ll	Hexagon: Add V4 combine instructions and some more Def Pats for V2.	2013-02-04 15:52:56 +00:00
combine.ll
convertdptoint.ll
convertdptoll.ll
convertsptoint.ll
convertsptoll.ll
dadd.ll
dmul.ll
double.ll
doubleconvert-ieee-rnd-near.ll
dsub.ll
dualstore.ll
fadd.ll
fcmp.ll
float.ll
floatconvert-ieee-rnd-near.ll
fmul.ll
frame.ll
fsub.ll
fusedandshift.ll
idxload-with-zero-offset.ll
lit.local.cfg
macint.ll
mpy.ll
newvaluejump2.ll
newvaluejump.ll
newvaluestore.ll
opt-fabs.ll
opt-fneg.ll
postinc-load.ll
postinc-store.ll	Hexagon: Add testcase for post-increment store instructions.	2013-02-05 18:23:51 +00:00
remove_lsr.ll
simpletailcall.ll
static.ll
struct_args_large.ll
struct_args.ll	Hexagon: Add V4 combine instructions and some more Def Pats for V2.	2013-02-04 15:52:56 +00:00
vaddh.ll
validate-offset.ll