Bob Wilson dc66edaced Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee ...

that the high halfword is zero.  The shift need not be exactly 16 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111196 91177308-0d34-0410-b5e6-96231b3b80d8

2010-08-16 22:26:55 +00:00

..

Alpha

PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually

2010-08-01 21:13:28 +00:00

ARM

Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee

2010-08-16 22:26:55 +00:00

Blackfin

Remove TargetInstrInfo::copyRegToReg entirely.

2010-07-11 17:01:17 +00:00

CBackend

…

CellSPU

Have SPU handle halfvec stores aligned by 8 bytes.

2010-08-09 16:33:00 +00:00

CPP

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Generic

Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself

2010-07-27 18:02:18 +00:00

MBlaze

Split big test into multiple directories to cater to

2010-04-07 20:43:35 +00:00

Mips

Fix PR7174, a couple o Mips fixes:

2010-07-20 08:37:04 +00:00

MSP430

Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1),

2010-05-01 12:52:34 +00:00

PIC16

Remove XFAIL for vg_leak as the leaks are fixed by 100601.

2010-04-07 07:06:48 +00:00

PowerPC

PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.

2010-08-02 00:18:19 +00:00

SPARC

Split big test into multiple directories to cater to

2010-04-07 20:43:35 +00:00

SystemZ

SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and

2010-05-14 22:17:42 +00:00

Thumb

Fix test and re-enable it.

2010-08-11 17:25:51 +00:00

Thumb2

Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee

2010-08-16 22:26:55 +00:00

X86

Test expects SSE, give him SSE.

2010-08-15 23:32:03 +00:00

XCore

Start function numbering at 0.

2010-04-17 16:29:15 +00:00